From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: Wed, 28 May 2014 07:28:21 +0000 (+0100)
Subject: apb: fix IOMMU register sizes
X-Git-Tag: TizenStudio_2.0_p2.3.2~208^2~802^2~2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fd7fbc8ff713ebf8fa2ae5078f1024079bde90b1;p=sdk%2Femulator%2Fqemu.git

apb: fix IOMMU register sizes

According to the referenced documentation, the IOMMU has 3 64-bit registers
consisting of a control register, base register and flush register.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---

diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index bea7092..e25791f 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -71,7 +71,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
 #define NO_IRQ_REQUEST (MAX_IVEC + 1)
 
 typedef struct IOMMUState {
-    uint32_t regs[4];
+    uint32_t regs[6];
 } IOMMUState;
 
 #define TYPE_APB "pbm"
@@ -157,11 +157,9 @@ static void apb_config_writel (void *opaque, hwaddr addr,
     case 0x30 ... 0x4f: /* DMA error registers */
         /* XXX: not implemented yet */
         break;
-    case 0x200 ... 0x20b: /* IOMMU */
+    case 0x200 ... 0x217: /* IOMMU */
         is->regs[(addr & 0xf) >> 2] = val;
         break;
-    case 0x20c ... 0x3ff: /* IOMMU flush */
-        break;
     case 0xc00 ... 0xc3f: /* PCI interrupt control */
         if (addr & 4) {
             unsigned int ino = (addr & 0x3f) >> 3;
@@ -241,12 +239,9 @@ static uint64_t apb_config_readl (void *opaque,
         val = 0;
         /* XXX: not implemented yet */
         break;
-    case 0x200 ... 0x20b: /* IOMMU */
+    case 0x200 ... 0x217: /* IOMMU */
         val = is->regs[(addr & 0xf) >> 2];
         break;
-    case 0x20c ... 0x3ff: /* IOMMU flush */
-        val = 0;
-        break;
     case 0xc00 ... 0xc3f: /* PCI interrupt control */
         if (addr & 4) {
             val = s->pci_irq_map[(addr & 0x3f) >> 3];