From: kyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu, 28 Aug 2014 06:34:06 +0000 (+0000)
Subject: AVX-512. Add vps[rl]ldq insn patterns.
X-Git-Tag: upstream/5.3.0~5879
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fd6b07be1eb6f69e870dbb98ca889b3960227881;p=platform%2Fupstream%2Flinaro-gcc.git

AVX-512. Add vps[rl]ldq insn patterns.

gcc/
	* config/i386/sse.md
	(define_mode_iterator VIMAX_AVX2): Add V4TI mode.
	(define_insn "<sse2_avx2>_ashl<mode>3"): Add EVEX version.
	(define_insn "<sse2_avx2>_lshr<mode>3"): Ditto.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214670 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 326919a..4054c09 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -8,6 +8,20 @@
 	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 
 	* config/i386/sse.md
+	(define_mode_iterator VIMAX_AVX2): Add V4TI mode.
+	(define_insn "<sse2_avx2>_ashl<mode>3"): Add EVEX version.
+	(define_insn "<sse2_avx2>_lshr<mode>3"): Ditto.
+
+2014-08-28  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+	    Anna Tikhonova  <anna.tikhonova@intel.com>
+	    Ilya Tocar  <ilya.tocar@intel.com>
+	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
+	    Ilya Verbin  <ilya.verbin@intel.com>
+	    Kirill Yukhin  <kirill.yukhin@intel.com>
+	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* config/i386/sse.md
 	(define_mode_iterator VI128_256): New.
 	(define_insn "<mask_codefor><code><mode>3<mask_name>"): Ditto.
 
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 6c99d84..a208400 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -331,7 +331,7 @@
 
 ;; ??? We should probably use TImode instead.
 (define_mode_iterator VIMAX_AVX2
-  [(V2TI "TARGET_AVX2") V1TI])
+  [(V4TI "TARGET_AVX512BW") (V2TI "TARGET_AVX2") V1TI])
 
 ;; ??? This should probably be dropped in favor of VIMAX_AVX2.
 (define_mode_iterator SSESCALARMODE
@@ -8819,9 +8819,9 @@
 })
 
 (define_insn "<sse2_avx2>_ashl<mode>3"
-  [(set (match_operand:VIMAX_AVX2 0 "register_operand" "=x,x")
+  [(set (match_operand:VIMAX_AVX2 0 "register_operand" "=x,v")
 	(ashift:VIMAX_AVX2
-	 (match_operand:VIMAX_AVX2 1 "register_operand" "0,x")
+	 (match_operand:VIMAX_AVX2 1 "register_operand" "0,v")
 	 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n,n")))]
   "TARGET_SSE2"
 {
@@ -8858,9 +8858,9 @@
 })
 
 (define_insn "<sse2_avx2>_lshr<mode>3"
-  [(set (match_operand:VIMAX_AVX2 0 "register_operand" "=x,x")
+  [(set (match_operand:VIMAX_AVX2 0 "register_operand" "=x,v")
 	(lshiftrt:VIMAX_AVX2
-	 (match_operand:VIMAX_AVX2 1 "register_operand" "0,x")
+	 (match_operand:VIMAX_AVX2 1 "register_operand" "0,v")
 	 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n,n")))]
   "TARGET_SSE2"
 {