From: Paul Berry Date: Mon, 5 Dec 2011 21:52:16 +0000 (-0800) Subject: i965 gen6+: Use 1-wide null operands for IF instructions X-Git-Tag: 062012170305~2652 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fd5d0c8b12a0e144aa8e95540c0da2161d8e089a;p=profile%2Fivi%2Fmesa.git i965 gen6+: Use 1-wide null operands for IF instructions The Sandy Bridge PRM, volume 4, part 2, section 5.3.10 ("5.3.10 Register Region Restrictions") contains the following restriction on the execution size and operand width of instructions: "3. ExecSize must be equal to or greater than Width." When emitting an IF instruction in single program flow mode on Gen6+, we use an ExecSize of 1, therefore the Width of each operand must also be 1. Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index a46a81b..d48753c 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -941,11 +941,11 @@ brw_IF(struct brw_compile *p, GLuint execute_size) } else if (intel->gen == 6) { brw_set_dest(p, insn, brw_imm_w(0)); insn->bits1.branch_gen6.jump_count = 0; - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); + brw_set_src1(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); } else { - brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); + brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); brw_set_src1(p, insn, brw_imm_ud(0)); insn->bits3.break_cont.jip = 0; insn->bits3.break_cont.uip = 0;