From: Eric Christopher <echristo@gmail.com>
Date: Tue, 28 Mar 2017 23:03:19 +0000 (+0000)
Subject: Default enable the rtm feature only on skylake and later for now because Intel disabl... 
X-Git-Tag: llvmorg-5.0.0-rc1~8996
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fc6ffede655b55099550b96604add2d1eb7877b0;p=platform%2Fupstream%2Fllvm.git

Default enable the rtm feature only on skylake and later for now because Intel disabled the feature on some haswell and broadwell processors:

http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf

the -mrtm option will still work normally.

llvm-svn: 298956
---

diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index 23ef9f8..d80a8d5 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -3194,6 +3194,7 @@ bool X86TargetInfo::initFeatureMap(
     setFeatureEnabledImpl(Features, "mpx", true);
     setFeatureEnabledImpl(Features, "sgx", true);
     setFeatureEnabledImpl(Features, "clflushopt", true);
+    setFeatureEnabledImpl(Features, "rtm", true);
     LLVM_FALLTHROUGH;
   case CK_Broadwell:
     setFeatureEnabledImpl(Features, "rdseed", true);
@@ -3204,7 +3205,6 @@ bool X86TargetInfo::initFeatureMap(
     setFeatureEnabledImpl(Features, "lzcnt", true);
     setFeatureEnabledImpl(Features, "bmi", true);
     setFeatureEnabledImpl(Features, "bmi2", true);
-    setFeatureEnabledImpl(Features, "rtm", true);
     setFeatureEnabledImpl(Features, "fma", true);
     setFeatureEnabledImpl(Features, "movbe", true);
     LLVM_FALLTHROUGH;
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index b63b6dd..5252d2c 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -525,7 +525,6 @@
 // CHECK_CORE_AVX2_M32: #define __PCLMUL__ 1
 // CHECK_CORE_AVX2_M32: #define __POPCNT__ 1
 // CHECK_CORE_AVX2_M32: #define __RDRND__ 1
-// CHECK_CORE_AVX2_M32: #define __RTM__ 1
 // CHECK_CORE_AVX2_M32: #define __SSE2__ 1
 // CHECK_CORE_AVX2_M32: #define __SSE3__ 1
 // CHECK_CORE_AVX2_M32: #define __SSE4_1__ 1
@@ -555,7 +554,6 @@
 // CHECK_CORE_AVX2_M64: #define __PCLMUL__ 1
 // CHECK_CORE_AVX2_M64: #define __POPCNT__ 1
 // CHECK_CORE_AVX2_M64: #define __RDRND__ 1
-// CHECK_CORE_AVX2_M64: #define __RTM__ 1
 // CHECK_CORE_AVX2_M64: #define __SSE2_MATH__ 1
 // CHECK_CORE_AVX2_M64: #define __SSE2__ 1
 // CHECK_CORE_AVX2_M64: #define __SSE3__ 1
@@ -591,7 +589,6 @@
 // CHECK_BROADWELL_M32: #define __POPCNT__ 1
 // CHECK_BROADWELL_M32: #define __RDRND__ 1
 // CHECK_BROADWELL_M32: #define __RDSEED__ 1
-// CHECK_BROADWELL_M32: #define __RTM__ 1
 // CHECK_BROADWELL_M32: #define __SSE2__ 1
 // CHECK_BROADWELL_M32: #define __SSE3__ 1
 // CHECK_BROADWELL_M32: #define __SSE4_1__ 1
@@ -623,7 +620,6 @@
 // CHECK_BROADWELL_M64: #define __POPCNT__ 1
 // CHECK_BROADWELL_M64: #define __RDRND__ 1
 // CHECK_BROADWELL_M64: #define __RDSEED__ 1
-// CHECK_BROADWELL_M64: #define __RTM__ 1
 // CHECK_BROADWELL_M64: #define __SSE2_MATH__ 1
 // CHECK_BROADWELL_M64: #define __SSE2__ 1
 // CHECK_BROADWELL_M64: #define __SSE3__ 1