From: Samuel Pitoiset Date: Thu, 7 Dec 2017 10:39:46 +0000 (+0100) Subject: radv: fix TC-compat HTILE with VK_FORMAT_D32_SFLOAT_S8_UINT on Vega X-Git-Tag: upstream/18.1.0~3342 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fc6c77e162df3405e6de9f5644788984b2f7aacc;p=platform%2Fupstream%2Fmesa.git radv: fix TC-compat HTILE with VK_FORMAT_D32_SFLOAT_S8_UINT on Vega Copied from RadeonSI. This fixes all CTS dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.clear.* And some other ones which use the same format. Signed-off-by: Samuel Pitoiset Reviewed-by: Dave Airlie --- diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 5c53e81..efd17e4 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -416,6 +416,12 @@ si_make_texture_descriptor(struct radv_device *device, data_format = 0; } + /* S8 with Z32 HTILE needs a special format. */ + if (device->physical_device->rad_info.chip_class >= GFX9 && + vk_format == VK_FORMAT_S8_UINT && + image->tc_compatible_htile) + data_format = V_008F14_IMG_DATA_FORMAT_S8_32; + type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples, is_storage_image, device->physical_device->rad_info.chip_class >= GFX9); if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {