From: Tilmann Scheller <t.scheller@samsung.com>
Date: Tue, 15 Jul 2014 16:33:24 +0000 (+0000)
Subject: [AArch64] Add negative tests for the SIMD & FP LDP instructions.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fc14cefeeade17a88822edd9d7ff2944067541c6;p=platform%2Fupstream%2Fllvm.git

[AArch64] Add negative tests for the SIMD & FP LDP instructions.

LDP is unpredictable if the registers in the pair are identical, these tests check that we don't assemble instructions like that and error out instead.

llvm-svn: 213074
---

diff --git a/llvm/test/MC/AArch64/arm64-diags.s b/llvm/test/MC/AArch64/arm64-diags.s
index cf00e982..f8138bd 100644
--- a/llvm/test/MC/AArch64/arm64-diags.s
+++ b/llvm/test/MC/AArch64/arm64-diags.s
@@ -159,6 +159,15 @@ ldr    q1, [x3, w3, sxtw #1]
   ldp w1, w2, [x2], #16
   ldp w2, w2, [x2], #16
   ldp x1, x1, [x2]
+  ldp s1, s1, [x1], #8
+  ldp s1, s1, [x1, #8]!
+  ldp s1, s1, [x1, #8]
+  ldp d1, d1, [x1], #16
+  ldp d1, d1, [x1, #16]!
+  ldp d1, d1, [x1, #16]
+  ldp q1, q1, [x1], #32
+  ldp q1, q1, [x1, #32]!
+  ldp q1, q1, [x1, #32]
 
   ldr x2, [x2], #8
   ldr x2, [x2, #8]!
@@ -185,6 +194,33 @@ ldr    q1, [x3, w3, sxtw #1]
 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 ; CHECK-ERRORS:   ldp x1, x1, [x2]
 ; CHECK-ERRORS:           ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
+; CHECK-ERRORS:   ldp s1, s1, [x1], #8
+; CHECK-ERRORS:           ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
+; CHECK-ERRORS:   ldp s1, s1, [x1, #8]!
+; CHECK-ERRORS:           ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
+; CHECK-ERRORS:   ldp s1, s1, [x1, #8]
+; CHECK-ERRORS:           ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
+; CHECK-ERRORS:   ldp d1, d1, [x1], #16
+; CHECK-ERRORS:           ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
+; CHECK-ERRORS:   ldp d1, d1, [x1, #16]!
+; CHECK-ERRORS:           ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
+; CHECK-ERRORS:   ldp d1, d1, [x1, #16]
+; CHECK-ERRORS:           ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
+; CHECK-ERRORS:   ldp q1, q1, [x1], #32
+; CHECK-ERRORS:           ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
+; CHECK-ERRORS:   ldp q1, q1, [x1, #32]!
+; CHECK-ERRORS:           ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
+; CHECK-ERRORS:   ldp q1, q1, [x1, #32]
+; CHECK-ERRORS:           ^
 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
 ; CHECK-ERRORS:   ldr x2, [x2], #8
 ; CHECK-ERRORS:       ^