From: Krzysztof Kozlowski Date: Thu, 19 Jan 2023 10:54:34 +0000 (+0100) Subject: arm64: dts: qcom: sm8350: fixup SDHCI interconnect arguments X-Git-Tag: v6.6.7~3530^2~3^2~20 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fc0ff3e702013c8af39f9967daaef1e565f7d165;p=platform%2Fkernel%2Flinux-starfive.git arm64: dts: qcom: sm8350: fixup SDHCI interconnect arguments After switching interconnects to 2 cells, the SDHCI interconnects need to get one more argument. Fixes: 4f287e31ff5f ("arm64: dts: qcom: sm8350: Use 2 interconnect cells") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230119105434.51635-1-krzysztof.kozlowski@linaro.org --- diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 3e019f8b..0a42263 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2547,8 +2547,8 @@ <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; resets = <&gcc GCC_SDCC2_BCR>; - interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; iommus = <&apps_smmu 0x4a0 0x0>; power-domains = <&rpmhpd SM8350_CX>;