From: David Daney <ddaney@caviumnetworks.com>
Date: Wed, 13 May 2009 22:59:55 +0000 (-0700)
Subject: MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.
X-Git-Tag: v2.6.31-rc1~291^2~2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fbeda19f82aa07082d2e1607a9f5114141dae2ac;p=platform%2Fkernel%2Flinux-3.10.git

MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.

Some CPUs have implementation dependent rdhwr registers.  Allow them
to be enabled on a per CPU basis.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1cba4b2..8ab1d12 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -234,4 +234,8 @@
 #define cpu_scache_line_size()	cpu_data[0].scache.linesz
 #endif
 
+#ifndef cpu_hwrena_impl_bits
+#define cpu_hwrena_impl_bits		0
+#endif
+
 #endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e83da17..f548717 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1502,7 +1502,7 @@ void __cpuinit per_cpu_trap_init(void)
 			 status_set);
 
 	if (cpu_has_mips_r2) {
-		unsigned int enable = 0x0000000f;
+		unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
 
 		if (!noulri && cpu_has_userlocal)
 			enable |= (1 << 29);