From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sat, 30 Jul 2016 20:28:02 +0000 (+0000)
Subject: [X86][SSE] Regenerate vshift tests
X-Git-Tag: llvmorg-4.0.0-rc1~13737
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fbe0fcb009b3e633d298408e32cd392542a16a6c;p=platform%2Fupstream%2Fllvm.git

[X86][SSE] Regenerate vshift tests

llvm-svn: 277278
---

diff --git a/llvm/test/CodeGen/X86/vshift-1.ll b/llvm/test/CodeGen/X86/vshift-1.ll
index b8a6767..7ad5706 100644
--- a/llvm/test/CodeGen/X86/vshift-1.ll
+++ b/llvm/test/CodeGen/X86/vshift-1.ll
@@ -1,22 +1,49 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
 
 ; test vector shifts converted to proper SSE2 vector shifts when the shift
 ; amounts are the same.
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
+; X32-LABEL: shift1a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    psllq $32, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift1a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    psllq $32, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift1a:
-; CHECK: psllq
   %shl = shl <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %shl, <2 x i64>* %dst
   ret void
 }
 
 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
+; X32-LABEL: shift1b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; X32-NEXT:    movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X32-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1]
+; X32-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; X32-NEXT:    psllq %xmm2, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift1b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movd %rsi, %xmm1
+; X64-NEXT:    psllq %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift1b:
-; CHECK: movd
-; CHECK: psllq
   %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
   %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
   %shl = shl <2 x i64> %val, %1
@@ -26,19 +53,40 @@ entry:
 
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+; X32-LABEL: shift2a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    pslld $5, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    pslld $5, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2a:
-; CHECK: pslld
   %shl = shl <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
   store <4 x i32> %shl, <4 x i32>* %dst
   ret void
 }
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+; X32-LABEL: shift2b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    pslld %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movd %esi, %xmm1
+; X64-NEXT:    pslld %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2b:
-; CHECK: movd
-; CHECK: pslld
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
   %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
   %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
@@ -49,9 +97,19 @@ entry:
 }
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
+; X32-LABEL: shift3a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    psllw $5, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift3a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    psllw $5, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift3a:
-; CHECK: psllw
   %shl = shl <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %shl, <8 x i16>* %dst
   ret void
@@ -59,11 +117,23 @@ entry:
 
 ; Make sure the shift amount is properly zero extended.
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+; X32-LABEL: shift3b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movd %ecx, %xmm1
+; X32-NEXT:    psllw %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift3b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movzwl %si, %eax
+; X64-NEXT:    movd %eax, %xmm1
+; X64-NEXT:    psllw %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift3b:
-; CHECK: movzwl
-; CHECK: movd
-; CHECK-NEXT: psllw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
   %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
   %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
diff --git a/llvm/test/CodeGen/X86/vshift-2.ll b/llvm/test/CodeGen/X86/vshift-2.ll
index 156649a..f79fc5b 100644
--- a/llvm/test/CodeGen/X86/vshift-2.ll
+++ b/llvm/test/CodeGen/X86/vshift-2.ll
@@ -1,22 +1,49 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
 
 ; test vector shifts converted to proper SSE2 vector shifts when the shift
 ; amounts are the same.
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
+; X32-LABEL: shift1a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    psrlq $32, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift1a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    psrlq $32, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift1a:
-; CHECK: psrlq
   %lshr = lshr <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %lshr, <2 x i64>* %dst
   ret void
 }
 
 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
+; X32-LABEL: shift1b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
+; X32-NEXT:    movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X32-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1]
+; X32-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
+; X32-NEXT:    psrlq %xmm2, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift1b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movd %rsi, %xmm1
+; X64-NEXT:    psrlq %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift1b:
-; CHECK: movd
-; CHECK: psrlq
   %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
   %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
   %lshr = lshr <2 x i64> %val, %1
@@ -25,19 +52,40 @@ entry:
 }
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+; X32-LABEL: shift2a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    psrld $17, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    psrld $17, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2a:
-; CHECK: psrld
   %lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 >
   store <4 x i32> %lshr, <4 x i32>* %dst
   ret void
 }
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+; X32-LABEL: shift2b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    psrld %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movd %esi, %xmm1
+; X64-NEXT:    psrld %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2b:
-; CHECK: movd
-; CHECK: psrld
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
   %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
   %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
@@ -49,9 +97,19 @@ entry:
 
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
+; X32-LABEL: shift3a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    psrlw $5, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift3a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    psrlw $5, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift3a:
-; CHECK: psrlw
   %lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %lshr, <8 x i16>* %dst
   ret void
@@ -59,11 +117,23 @@ entry:
 
 ; properly zero extend the shift amount
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+; X32-LABEL: shift3b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movd %ecx, %xmm1
+; X32-NEXT:    psrlw %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift3b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movzwl %si, %eax
+; X64-NEXT:    movd %eax, %xmm1
+; X64-NEXT:    psrlw %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift3b:
-; CHECK: movzwl
-; CHECK: movd
-; CHECK: psrlw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
   %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
   %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
diff --git a/llvm/test/CodeGen/X86/vshift-3.ll b/llvm/test/CodeGen/X86/vshift-3.ll
index f368029e..c59dace 100644
--- a/llvm/test/CodeGen/X86/vshift-3.ll
+++ b/llvm/test/CodeGen/X86/vshift-3.ll
@@ -1,4 +1,6 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
 
 ; test vector shifts converted to proper SSE2 vector shifts when the shift
 ; amounts are the same.
@@ -6,28 +8,65 @@
 ; Note that x86 does have ashr
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
+; X32-LABEL: shift1a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; X32-NEXT:    psrad $31, %xmm0
+; X32-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; X32-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; X32-NEXT:    movdqa %xmm1, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift1a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
+; X64-NEXT:    psrad $31, %xmm0
+; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
+; X64-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; X64-NEXT:    movdqa %xmm1, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift1a:
-; CHECK: psrad $31
   %ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %ashr, <2 x i64>* %dst
   ret void
 }
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
+; X32-LABEL: shift2a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    psrad $5, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    psrad $5, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2a:
-; CHECK: psrad	$5
   %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
   store <4 x i32> %ashr, <4 x i32>* %dst
   ret void
 }
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+; X32-LABEL: shift2b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    psrad %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movd %esi, %xmm1
+; X64-NEXT:    psrad %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2b:
-; CHECK: movd
-; CHECK: psrad
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
   %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
   %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
@@ -38,20 +77,42 @@ entry:
 }
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
+; X32-LABEL: shift3a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    psraw $5, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift3a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    psraw $5, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift3a:
-; CHECK: psraw	$5
   %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %ashr, <8 x i16>* %dst
   ret void
 }
 
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+; X32-LABEL: shift3b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movd %ecx, %xmm1
+; X32-NEXT:    psraw %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift3b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movzwl %si, %eax
+; X64-NEXT:    movd %eax, %xmm1
+; X64-NEXT:    psraw %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift3b:
-; CHECK: movzwl
-; CHECK: movd
-; CHECK: psraw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
   %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
   %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
diff --git a/llvm/test/CodeGen/X86/vshift-4.ll b/llvm/test/CodeGen/X86/vshift-4.ll
index 4ab5db8..4e5fb60 100644
--- a/llvm/test/CodeGen/X86/vshift-4.ll
+++ b/llvm/test/CodeGen/X86/vshift-4.ll
@@ -1,12 +1,25 @@
-; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
 
 ; test vector shifts converted to proper SSE2 vector shifts when the shift
 ; amounts are the same when using a shuffle splat.
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
+; X32-LABEL: shift1a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movq {{.*#+}} xmm1 = xmm1[0],zero
+; X32-NEXT:    psllq %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift1a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    psllq %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift1a:
-; CHECK: psllq
   %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
   %shl = shl <2 x i64> %val, %shamt
   store <2 x i64> %shl, <2 x i64>* %dst
@@ -15,14 +28,28 @@ entry:
 
 ; shift1b can't use a packed shift but can shift lanes separately and shuffle back together
 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
+; X32-LABEL: shift1b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
+; X32-NEXT:    movdqa %xmm0, %xmm3
+; X32-NEXT:    psllq %xmm2, %xmm3
+; X32-NEXT:    movq {{.*#+}} xmm1 = xmm1[0],zero
+; X32-NEXT:    psllq %xmm1, %xmm0
+; X32-NEXT:    movsd {{.*#+}} xmm3 = xmm0[0],xmm3[1]
+; X32-NEXT:    movapd %xmm3, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift1b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
+; X64-NEXT:    movdqa %xmm0, %xmm3
+; X64-NEXT:    psllq %xmm2, %xmm3
+; X64-NEXT:    psllq %xmm1, %xmm0
+; X64-NEXT:    movsd {{.*#+}} xmm3 = xmm0[0],xmm3[1]
+; X64-NEXT:    movapd %xmm3, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift1b:
-; CHECK:       pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
-; CHECK-NEXT:  movdqa %xmm0, %xmm3
-; CHECK-NEXT:  psllq  %xmm2, %xmm3
-; CHECK-NEXT:  movq   {{.*#+}} xmm1 = xmm1[0],zero
-; CHECK-NEXT:  psllq  %xmm1, %xmm0
-; CHECK-NEXT:  movsd  {{.*#+}} xmm3 = xmm0[0],xmm3[1]
   %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
   %shl = shl <2 x i64> %val, %shamt
   store <2 x i64> %shl, <2 x i64>* %dst
@@ -30,9 +57,25 @@ entry:
 }
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
+; X32-LABEL: shift2a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; X32-NEXT:    xorps %xmm2, %xmm2
+; X32-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; X32-NEXT:    pslld %xmm2, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; X64-NEXT:    xorps %xmm2, %xmm2
+; X64-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; X64-NEXT:    pslld %xmm2, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2a:
-; CHECK: pslld
   %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %shl = shl <4 x i32> %val, %shamt
   store <4 x i32> %shl, <4 x i32>* %dst
@@ -40,9 +83,25 @@ entry:
 }
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
+; X32-LABEL: shift2b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; X32-NEXT:    xorps %xmm2, %xmm2
+; X32-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; X32-NEXT:    pslld %xmm2, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; X64-NEXT:    xorps %xmm2, %xmm2
+; X64-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; X64-NEXT:    pslld %xmm2, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2b:
-; CHECK: pslld
   %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
   %shl = shl <4 x i32> %val, %shamt
   store <4 x i32> %shl, <4 x i32>* %dst
@@ -50,9 +109,25 @@ entry:
 }
 
 define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
+; X32-LABEL: shift2c:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; X32-NEXT:    xorps %xmm2, %xmm2
+; X32-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; X32-NEXT:    pslld %xmm2, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift2c:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
+; X64-NEXT:    xorps %xmm2, %xmm2
+; X64-NEXT:    movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
+; X64-NEXT:    pslld %xmm2, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift2c:
-; CHECK: pslld
   %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %shl = shl <4 x i32> %val, %shamt
   store <4 x i32> %shl, <4 x i32>* %dst
@@ -60,10 +135,23 @@ entry:
 }
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
+; X32-LABEL: shift3a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    pextrw $6, %xmm1, %ecx
+; X32-NEXT:    movd %ecx, %xmm1
+; X32-NEXT:    psllw %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift3a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    pextrw $6, %xmm1, %eax
+; X64-NEXT:    movd %eax, %xmm1
+; X64-NEXT:    psllw %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift3a:
-; CHECK: pextrw $6
-; CHECK: psllw
   %shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
   %shl = shl <8 x i16> %val, %shamt
   store <8 x i16> %shl, <8 x i16>* %dst
@@ -71,10 +159,23 @@ entry:
 }
 
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
+; X32-LABEL: shift3b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movd %ecx, %xmm1
+; X32-NEXT:    psllw %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift3b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movzwl %si, %eax
+; X64-NEXT:    movd %eax, %xmm1
+; X64-NEXT:    psllw %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift3b:
-; CHECK: movzwl
-; CHECK: psllw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
   %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
   %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
diff --git a/llvm/test/CodeGen/X86/vshift-5.ll b/llvm/test/CodeGen/X86/vshift-5.ll
index a6ae8d5..38b391b 100644
--- a/llvm/test/CodeGen/X86/vshift-5.ll
+++ b/llvm/test/CodeGen/X86/vshift-5.ll
@@ -1,15 +1,29 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
 
 ; When loading the shift amount from memory, avoid generating the splat.
 
 define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
+; X32-LABEL: shift5a:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    pslld %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift5a:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X64-NEXT:    pslld %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift5a:
-; CHECK: movd
-; CHECK: pslld
-  %amt = load i32, i32* %pamt 
+  %amt = load i32, i32* %pamt
   %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
-  %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer 
+  %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
   %shl = shl <4 x i32> %val, %shamt
   store <4 x i32> %shl, <4 x i32>* %dst
   ret void
@@ -17,13 +31,25 @@ entry:
 
 
 define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
+; X32-LABEL: shift5b:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    psrad %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift5b:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X64-NEXT:    psrad %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift5b:
-; CHECK: movd
-; CHECK: psrad
-  %amt = load i32, i32* %pamt 
+  %amt = load i32, i32* %pamt
   %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
-  %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer 
+  %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
   %shr = ashr <4 x i32> %val, %shamt
   store <4 x i32> %shr, <4 x i32>* %dst
   ret void
@@ -31,10 +57,21 @@ entry:
 
 
 define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+; X32-LABEL: shift5c:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    pslld %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift5c:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movd %esi, %xmm1
+; X64-NEXT:    pslld %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift5c:
-; CHECK: movd
-; CHECK: pslld
   %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
   %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
   %shl = shl <4 x i32> %val, %shamt
@@ -44,10 +81,21 @@ entry:
 
 
 define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
+; X32-LABEL: shift5d:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT:    psrad %xmm1, %xmm0
+; X32-NEXT:    movdqa %xmm0, (%eax)
+; X32-NEXT:    retl
+;
+; X64-LABEL: shift5d:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movd %esi, %xmm1
+; X64-NEXT:    psrad %xmm1, %xmm0
+; X64-NEXT:    movdqa %xmm0, (%rdi)
+; X64-NEXT:    retq
 entry:
-; CHECK-LABEL: shift5d:
-; CHECK: movd
-; CHECK: psrad
   %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
   %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
   %shr = ashr <4 x i32> %val, %shamt
diff --git a/llvm/test/CodeGen/X86/vshift-6.ll b/llvm/test/CodeGen/X86/vshift-6.ll
index 551a138..36d428c 100644
--- a/llvm/test/CodeGen/X86/vshift-6.ll
+++ b/llvm/test/CodeGen/X86/vshift-6.ll
@@ -1,4 +1,6 @@
-; RUN: llc < %s -march=x86-64 -mattr=+sse2  | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
 
 ; This test makes sure that the compiler does not crash with an
 ; assertion failure when trying to fold a vector shift left
@@ -23,6 +25,77 @@
 ; 'count' is the vector shift count.
 
 define <16 x i8> @do_not_crash(i8*, i32*, i64*, i32, i64, i8) {
+; X32-LABEL: do_not_crash:
+; X32:       # BB#0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movb %al, (%ecx)
+; X32-NEXT:    movd %eax, %xmm0
+; X32-NEXT:    psllq $56, %xmm0
+; X32-NEXT:    movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255]
+; X32-NEXT:    movdqa %xmm2, %xmm1
+; X32-NEXT:    pandn %xmm0, %xmm1
+; X32-NEXT:    por %xmm2, %xmm1
+; X32-NEXT:    pcmpeqd %xmm2, %xmm2
+; X32-NEXT:    psllw $5, %xmm1
+; X32-NEXT:    pxor %xmm3, %xmm3
+; X32-NEXT:    pxor %xmm0, %xmm0
+; X32-NEXT:    pcmpgtb %xmm1, %xmm0
+; X32-NEXT:    pxor %xmm0, %xmm2
+; X32-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-NEXT:    por %xmm2, %xmm0
+; X32-NEXT:    paddb %xmm1, %xmm1
+; X32-NEXT:    pxor %xmm2, %xmm2
+; X32-NEXT:    pcmpgtb %xmm1, %xmm2
+; X32-NEXT:    movdqa %xmm2, %xmm4
+; X32-NEXT:    pandn %xmm0, %xmm4
+; X32-NEXT:    psllw $2, %xmm0
+; X32-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-NEXT:    pand %xmm2, %xmm0
+; X32-NEXT:    por %xmm4, %xmm0
+; X32-NEXT:    paddb %xmm1, %xmm1
+; X32-NEXT:    pcmpgtb %xmm1, %xmm3
+; X32-NEXT:    movdqa %xmm3, %xmm1
+; X32-NEXT:    pandn %xmm0, %xmm1
+; X32-NEXT:    paddb %xmm0, %xmm0
+; X32-NEXT:    pand %xmm3, %xmm0
+; X32-NEXT:    por %xmm1, %xmm0
+; X32-NEXT:    retl
+;
+; X64-LABEL: do_not_crash:
+; X64:       # BB#0: # %entry
+; X64-NEXT:    movb %r9b, (%rdi)
+; X64-NEXT:    movd %r9d, %xmm0
+; X64-NEXT:    psllq $56, %xmm0
+; X64-NEXT:    movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,0,255,255,255,255,255,255,255,255]
+; X64-NEXT:    movdqa %xmm2, %xmm1
+; X64-NEXT:    pandn %xmm0, %xmm1
+; X64-NEXT:    por %xmm2, %xmm1
+; X64-NEXT:    pcmpeqd %xmm2, %xmm2
+; X64-NEXT:    psllw $5, %xmm1
+; X64-NEXT:    pxor %xmm3, %xmm3
+; X64-NEXT:    pxor %xmm0, %xmm0
+; X64-NEXT:    pcmpgtb %xmm1, %xmm0
+; X64-NEXT:    pxor %xmm0, %xmm2
+; X64-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-NEXT:    por %xmm2, %xmm0
+; X64-NEXT:    paddb %xmm1, %xmm1
+; X64-NEXT:    pxor %xmm2, %xmm2
+; X64-NEXT:    pcmpgtb %xmm1, %xmm2
+; X64-NEXT:    movdqa %xmm2, %xmm4
+; X64-NEXT:    pandn %xmm0, %xmm4
+; X64-NEXT:    psllw $2, %xmm0
+; X64-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-NEXT:    pand %xmm2, %xmm0
+; X64-NEXT:    por %xmm4, %xmm0
+; X64-NEXT:    paddb %xmm1, %xmm1
+; X64-NEXT:    pcmpgtb %xmm1, %xmm3
+; X64-NEXT:    movdqa %xmm3, %xmm1
+; X64-NEXT:    pandn %xmm0, %xmm1
+; X64-NEXT:    paddb %xmm0, %xmm0
+; X64-NEXT:    pand %xmm3, %xmm0
+; X64-NEXT:    por %xmm1, %xmm0
+; X64-NEXT:    retq
 entry:
   store i8 %5, i8* %0
   %L5 = load i8, i8* %0
@@ -30,7 +103,3 @@ entry:
   %B51 = shl <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, %I8
   ret <16 x i8> %B51
 }
-
-; CHECK-LABEL: do_not_crash
-; CHECK: ret
-