From: Aaron Ballman <aaron@aaronballman.com>
Date: Wed, 17 Jul 2013 19:43:13 +0000 (+0000)
Subject: Silencing an MSVC warning about signed vs unsigned comparison mismatches.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fbb104513ba7de25b74d71875328bf45c6f3277b;p=platform%2Fupstream%2Fllvm.git

Silencing an MSVC warning about signed vs unsigned comparison mismatches.

llvm-svn: 186529
---

diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index f5d5e5a..bf341b3 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -781,7 +781,7 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
   // all cases and are sometimes shorter.  Prefer to use RISBG for ANDs though,
   // since it is effectively a three-operand instruction in this case,
   // and since it can handle some masks that AND IMMEDIATE can't.
-  if (Count < (N->getOpcode() == ISD::AND ? 1 : 2))
+  if (Count < (N->getOpcode() == ISD::AND ? 1U : 2U))
     return 0;
 
   // Prefer register extensions like LLC over RISBG.