From: Stefan Pintilie Date: Tue, 28 Sep 2021 19:44:30 +0000 (-0500) Subject: [PowerPC] The builtins load8r and store8r are Power 7 plus. X-Git-Tag: upstream/15.0.7~30118 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fb4e44c4e7daaaa1d2776e76d43566b0db264f30;p=platform%2Fupstream%2Fllvm.git [PowerPC] The builtins load8r and store8r are Power 7 plus. This patch makes sure that the builtins __builtin_ppc_load8r and __ builtin_ppc_store8r are only available for Power 7 and up. Currently the builtins seem to produce incorrect code if used for Power 6 or before. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D110653 --- diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index 21376b3..26be2bd 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -73,6 +73,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector &Features, HasROPProtect = true; } else if (Feature == "+privileged") { HasPrivileged = true; + } else if (Feature == "+isa-v206-instructions") { + IsISA2_06 = true; } else if (Feature == "+isa-v207-instructions") { IsISA2_07 = true; } else if (Feature == "+isa-v30-instructions") { @@ -526,6 +528,13 @@ bool PPCTargetInfo::initFeatureMap( .Case("e500", true) .Default(false); + Features["isa-v206-instructions"] = llvm::StringSwitch(CPU) + .Case("ppc64le", true) + .Case("pwr9", true) + .Case("pwr8", true) + .Case("pwr7", true) + .Default(false); + Features["isa-v207-instructions"] = llvm::StringSwitch(CPU) .Case("ppc64le", true) .Case("pwr9", true) @@ -622,6 +631,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const { .Case("mma", HasMMA) .Case("rop-protect", HasROPProtect) .Case("privileged", HasPrivileged) + .Case("isa-v206-instructions", IsISA2_06) .Case("isa-v207-instructions", IsISA2_07) .Case("isa-v30-instructions", IsISA3_0) .Case("isa-v31-instructions", IsISA3_1) diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h index 8903468..f19d3eb 100644 --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -74,6 +74,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool HasP10Vector = false; bool HasPCRelativeMemops = false; bool HasPrefixInstrs = false; + bool IsISA2_06 = false; bool IsISA2_07 = false; bool IsISA3_0 = false; bool IsISA3_1 = false; diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index a6ea2bf..8b53e35 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -3512,6 +3512,10 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, diag::err_ppc_builtin_requires_vsx) || SemaBuiltinConstantArgRange(TheCall, 1, 0, 127); } + case PPC::BI__builtin_ppc_load8r: + case PPC::BI__builtin_ppc_store8r: + return SemaFeatureCheck(*this, TheCall, "isa-v206-instructions", + diag::err_ppc_builtin_only_on_arch, "7"); #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \ case PPC::BI__builtin_##Name: \ return SemaBuiltinPPCMMACall(TheCall, Types); diff --git a/clang/test/Driver/ppc-isa-features.cpp b/clang/test/Driver/ppc-isa-features.cpp index 9e2bc3f..87a3a80 100644 --- a/clang/test/Driver/ppc-isa-features.cpp +++ b/clang/test/Driver/ppc-isa-features.cpp @@ -1,8 +1,14 @@ +// RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr6 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR6 // RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr7 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR7 // RUN: %clang -target powerpc64le-unknown-unknown -mcpu=pwr8 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR8 // RUN: %clang -target powerpc64-unknown-aix -mcpu=pwr9 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR9 // RUN: %clang -target powerpc-unknown-aix -mcpu=pwr10 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR10 +// CHECK-PWR6: -isa-v206-instructions +// CHECK-PWR6: -isa-v207-instructions +// CHECK-PWR6: -isa-v30-instructions + +// CHECK-PWR7: +isa-v206-instructions // CHECK-PWR7: -isa-v207-instructions // CHECK-PWR7: -isa-v30-instructions diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index ce43ced..e41e013 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -213,6 +213,9 @@ def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", "Treat vector data stream cache control instructions as deprecated">; +def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06", + "true", + "Enable instructions in ISA 2.06.">; def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07", "true", "Enable instructions in ISA 2.07.">; @@ -319,7 +322,8 @@ def ProcessorFeatures { FeatureMFTB, DeprecatedDST, FeatureTwoConstNR, - FeatureUnalignedFloats]; + FeatureUnalignedFloats, + FeatureISA2_06]; list P7SpecificFeatures = []; list P7Features = !listconcat(P7InheritableFeatures, P7SpecificFeatures); diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 4ce9243..9d9e0e9 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -1302,9 +1302,12 @@ def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), "ldx $rD, $src", IIC_LdStLD, [(set i64:$rD, (load XForm:$src))]>, isPPC64; + +let Predicates = [IsISA2_06] in { def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), "ldbrx $rD, $src", IIC_LdStLoad, [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64; +} let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), @@ -1538,10 +1541,13 @@ def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), "stdx $rS, $dst", IIC_LdStSTD, [(store i64:$rS, XForm:$dst)]>, isPPC64, PPC970_DGroup_Cracked; + +let Predicates = [IsISA2_06] in { def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), "stdbrx $rS, $dst", IIC_LdStStore, [(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64, PPC970_DGroup_Cracked; +} let mayStore = 1, hasNoSchedulingInfo = 1 in { // Normal 16-byte stores. diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 03434ec..22f6464 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1182,6 +1182,7 @@ def NaNsFPMath : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; +def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; def HasFPU : Predicate<"Subtarget->hasFPU()">; diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp index 87ce32f..5fefd68 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -127,6 +127,7 @@ void PPCSubtarget::initializeEnvironment() { HasStoreFusion = false; HasAddiLoadFusion = false; HasAddisLoadFusion = false; + IsISA2_06 = false; IsISA2_07 = false; IsISA3_0 = false; IsISA3_1 = false; diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h index e916b0c..e2502ca 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -147,6 +147,7 @@ protected: bool HasStoreFusion; bool HasAddiLoadFusion; bool HasAddisLoadFusion; + bool IsISA2_06; bool IsISA2_07; bool IsISA3_0; bool IsISA3_1; @@ -322,6 +323,7 @@ public: bool hasHTM() const { return HasHTM; } bool hasFloat128() const { return HasFloat128; } + bool isISA2_06() const { return IsISA2_06; } bool isISA2_07() const { return IsISA2_07; } bool isISA3_0() const { return IsISA3_0; } bool isISA3_1() const { return IsISA3_1; }