From: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sun, 4 Jan 2015 23:03:20 +0000 (-0500)
Subject: nv50/ir: fix texture offsets in release builds
X-Git-Tag: upstream/17.1.0~21744
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fb1afd1ea5fd25d82c75c5c3a2aba0bcb53b6d47;p=platform%2Fupstream%2Fmesa.git

nv50/ir: fix texture offsets in release builds

assert's get compiled out in release builds, so they can't be relied
upon to perform logic.

Reported-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Roy Spliet <rspliet@eclipso.eu>
Cc: "10.2 10.3 10.4" <mesa-stable@lists.freedesktop.org>
---

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
index e283424..0d7612e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -772,7 +772,8 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
    if (i->tex.useOffsets) {
       for (int c = 0; c < 3; ++c) {
          ImmediateValue val;
-         assert(i->offset[0][c].getImmediate(val));
+         if (!i->offset[0][c].getImmediate(val))
+            assert(!"non-immediate offset");
          i->tex.offset[c] = val.reg.data.u32;
          i->offset[0][c].set(NULL);
       }
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 9c06d04..c234131 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -754,7 +754,8 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
          assert(i->tex.useOffsets == 1);
          for (c = 0; c < 3; ++c) {
             ImmediateValue val;
-            assert(i->offset[0][c].getImmediate(val));
+            if (!i->offset[0][c].getImmediate(val))
+               assert(!"non-immediate offset passed to non-TXG");
             imm |= (val.reg.data.u32 & 0xf) << (c * 4);
          }
          if (i->op == OP_TXD && chipset >= NVISA_GK104_CHIPSET) {