From: Chen-Yu Tsai Date: Mon, 22 May 2017 06:25:47 +0000 (+0800) Subject: clk: sunxi-ng: a83t: Fix PLL lock status register offset X-Git-Tag: v5.15~10942^2~34^2~5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=faea8b0e33c2e6a276d34a755258bb2176553616;p=platform%2Fkernel%2Flinux-starfive.git clk: sunxi-ng: a83t: Fix PLL lock status register offset The offset for the PLL lock status register was incorrectly set to 0x208, which actually points to an unused register. The correct register offset is 0x20c. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index 4a201a7..a9c5cc87 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -28,7 +28,7 @@ #include "ccu-sun8i-a83t.h" -#define CCU_SUN8I_A83T_LOCK_REG 0x208 +#define CCU_SUN8I_A83T_LOCK_REG 0x20c /* * The CPU PLLs are actually NP clocks, with P being /1 or /4. However