From: Joonyoung Shim <jy0922.shim@samsung.com>
Date: Wed, 8 Apr 2015 07:23:52 +0000 (+0900)
Subject: ARM: dts: exynos5420: fix clk of mali node
X-Git-Tag: submit/tizen/20160405.082219~159
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fabf317d829cf7db3b6e0d57a2c1c17c249bb1ed;p=platform%2Fkernel%2Flinux-exynos.git

ARM: dts: exynos5420: fix clk of mali node

Need only CLK_G3D gate clock for mali and use clk_mali name to control
the clock from mali core codes.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
---

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 7a4c14afd73f..e72c0c598308 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -918,11 +918,8 @@
 		reg = <0x11800000 0x5000>;
 		interrupts = <0 219 0>, <0 74 0>, <0 117 0>;
 		interrupt-names = "JOB", "MMU", "GPU";
-		clocks = <&clock CLK_G3D>, <&clock CLK_MOUT_G3D>,
-			 <&clock CLK_MOUT_VPLL>, <&clock CLK_FIN_PLL>,
-			 <&clock CLK_FOUT_VPLL>;
-		clock-names = "g3d", "aclk_g3d", "mout_vpll", "ext_xtal",
-			      "fout_vpll";
+		clocks = <&clock CLK_G3D>;
+		clock-names = "clk_mali";
 		status = "disabled";
 	};