From: Petar Avramovic <Petar.Avramovic@rt-rk.com>
Date: Thu, 6 Jun 2019 09:02:24 +0000 (+0000)
Subject: [MIPS GlobalISel] Select floor and ceil
X-Git-Tag: llvmorg-9.0.0-rc1~3674
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=faaa2b5d2156271d19603ebedfa80f10c3703d7f;p=platform%2Fupstream%2Fllvm.git

[MIPS GlobalISel] Select floor and ceil

Select G_FFLOOR and G_FCEIL for MIPS32.

Differential Revision: https://reviews.llvm.org/D62901

llvm-svn: 362688
---

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index f9e8c835662d..bb10291b6e7e 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -274,6 +274,12 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
     return Size == 128 ? RTLIB::LOG2_F128
                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
+  case TargetOpcode::G_FCEIL:
+    assert((Size == 32 || Size == 64) && "Unsupported size");
+    return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
+  case TargetOpcode::G_FFLOOR:
+    assert((Size == 32 || Size == 64) && "Unsupported size");
+    return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
   }
   llvm_unreachable("Unknown libcall function");
 }
@@ -372,7 +378,9 @@ LegalizerHelper::libcall(MachineInstr &MI) {
   case TargetOpcode::G_FLOG:
   case TargetOpcode::G_FLOG2:
   case TargetOpcode::G_FEXP:
-  case TargetOpcode::G_FEXP2: {
+  case TargetOpcode::G_FEXP2:
+  case TargetOpcode::G_FCEIL:
+  case TargetOpcode::G_FFLOOR: {
     if (Size > 64) {
       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
       return UnableToLegalize;
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index cabaed8e303b..4fb61ce457da 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -101,6 +101,9 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
       .legalFor({{s32, s32}, {s32, s64}})
       .minScalar(0, s32);
 
+  getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
+      .libcallFor({s32, s64});
+
   computeTables();
   verify(*ST.getInstrInfo());
 }
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir
new file mode 100644
index 000000000000..f7e39f3885b3
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ceil_and_floor.mir
@@ -0,0 +1,147 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+  define void @ceil_f32() {entry: ret void}
+  define void @ceil_f64() {entry: ret void}
+  define void @floor_f32() {entry: ret void}
+  define void @floor_f64() {entry: ret void}
+
+...
+---
+name:            ceil_f32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $f12
+
+    ; FP32-LABEL: name: ceil_f32
+    ; FP32: liveins: $f12
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $f12 = COPY [[COPY]](s32)
+    ; FP32: JAL &ceilf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $f0
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $f0 = COPY [[COPY1]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: ceil_f32
+    ; FP64: liveins: $f12
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $f12 = COPY [[COPY]](s32)
+    ; FP64: JAL &ceilf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $f0
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $f0 = COPY [[COPY1]](s32)
+    ; FP64: RetRA implicit $f0
+    %0:_(s32) = COPY $f12
+    %1:_(s32) = G_FCEIL %0
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            ceil_f64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $d6
+
+    ; FP32-LABEL: name: ceil_f64
+    ; FP32: liveins: $d6
+    ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $d6 = COPY [[COPY]](s64)
+    ; FP32: JAL &ceil, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $d0
+    ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $d0 = COPY [[COPY1]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: ceil_f64
+    ; FP64: liveins: $d6
+    ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $d12_64 = COPY [[COPY]](s64)
+    ; FP64: JAL &ceil, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $d0_64
+    ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0_64
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $d0 = COPY [[COPY1]](s64)
+    ; FP64: RetRA implicit $d0
+    %0:_(s64) = COPY $d6
+    %1:_(s64) = G_FCEIL %0
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...
+---
+name:            floor_f32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $f12
+
+    ; FP32-LABEL: name: floor_f32
+    ; FP32: liveins: $f12
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $f12 = COPY [[COPY]](s32)
+    ; FP32: JAL &floorf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $f0
+    ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $f0 = COPY [[COPY1]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: floor_f32
+    ; FP64: liveins: $f12
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $f12 = COPY [[COPY]](s32)
+    ; FP64: JAL &floorf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $f0
+    ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f0
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $f0 = COPY [[COPY1]](s32)
+    ; FP64: RetRA implicit $f0
+    %0:_(s32) = COPY $f12
+    %1:_(s32) = G_FFLOOR %0
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            floor_f64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $d6
+
+    ; FP32-LABEL: name: floor_f64
+    ; FP32: liveins: $d6
+    ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+    ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $d6 = COPY [[COPY]](s64)
+    ; FP32: JAL &floor, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit-def $d0
+    ; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
+    ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP32: $d0 = COPY [[COPY1]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: floor_f64
+    ; FP64: liveins: $d6
+    ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+    ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $d12_64 = COPY [[COPY]](s64)
+    ; FP64: JAL &floor, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $d12_64, implicit-def $d0_64
+    ; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0_64
+    ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+    ; FP64: $d0 = COPY [[COPY1]](s64)
+    ; FP64: RetRA implicit $d0
+    %0:_(s64) = COPY $d6
+    %1:_(s64) = G_FFLOOR %0
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll
new file mode 100644
index 000000000000..c3366430d617
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+
+declare float @llvm.ceil.f32(float)
+define float @ceil_f32(float %a) {
+; MIPS32-LABEL: ceil_f32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    jal ceilf
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = call float @llvm.ceil.f32(float %a)
+  ret float %0
+}
+
+declare double @llvm.ceil.f64(double)
+define double @ceil_f64(double %a) {
+; MIPS32-LABEL: ceil_f64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    jal ceil
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = call double @llvm.ceil.f64(double %a)
+  ret double %0
+}
+
+declare float @llvm.floor.f32(float)
+define float @floor_f32(float %a) {
+; MIPS32-LABEL: floor_f32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    jal floorf
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = call float @llvm.floor.f32(float %a)
+  ret float %0
+}
+
+declare double @llvm.floor.f64(double)
+define double @floor_f64(double %a) {
+; MIPS32-LABEL: floor_f64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    .cfi_offset 31, -4
+; MIPS32-NEXT:    jal floor
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = call double @llvm.floor.f64(double %a)
+  ret double %0
+}