From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Thu, 27 Jul 2023 06:43:02 +0000 (+0200)
Subject: radv: copy the number of TCS vertices out to TES shader info
X-Git-Tag: upstream/23.3.3~4966
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=faa756b3ba709302f9279f56acdd71aa94832bed;p=platform%2Fupstream%2Fmesa.git

radv: copy the number of TCS vertices out to TES shader info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24346>
---

diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c
index 6489a82..f422cc8 100644
--- a/src/amd/vulkan/nir/radv_nir_lower_abi.c
+++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c
@@ -150,7 +150,7 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
           */
          nir_ssa_def *arg = ac_nir_load_arg(b, &s->args->ac, s->args->ac.tes_rel_patch_id);
          nir_intrinsic_instr *load_arg = nir_instr_as_intrinsic(arg->parent_instr);
-         nir_intrinsic_set_arg_upper_bound_u32_amd(load_arg, 2048 / MAX2(b->shader->info.tess.tcs_vertices_out, 1));
+         nir_intrinsic_set_arg_upper_bound_u32_amd(load_arg, 2048 / MAX2(s->info->tes.tcs_vertices_out, 1));
          replacement = arg;
       } else {
          unreachable("invalid tessellation shader stage");
@@ -164,7 +164,7 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
             replacement = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_PATCH_CONTROL_POINTS);
          }
       } else if (stage == MESA_SHADER_TESS_EVAL) {
-         replacement = nir_imm_int(b, b->shader->info.tess.tcs_vertices_out);
+         replacement = nir_imm_int(b, s->info->tes.tcs_vertices_out);
       } else
          unreachable("invalid tessellation shader stage");
       break;
@@ -278,9 +278,16 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
       break;
    }
    case nir_intrinsic_load_hs_out_patch_data_offset_amd: {
-      unsigned out_vertices_per_patch = b->shader->info.tess.tcs_vertices_out;
+      unsigned out_vertices_per_patch;
       unsigned num_tcs_outputs =
          stage == MESA_SHADER_TESS_CTRL ? s->info->tcs.num_linked_outputs : s->info->tes.num_linked_inputs;
+
+      if (stage == MESA_SHADER_TESS_CTRL) {
+         out_vertices_per_patch = s->info->tcs.tcs_vertices_out;
+      } else {
+         out_vertices_per_patch = s->info->tes.tcs_vertices_out;
+      }
+
       int per_vertex_output_patch_size = out_vertices_per_patch * num_tcs_outputs * 16u;
 
       if (s->info->num_tess_patches) {
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index daaf011..df0f23d 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -346,6 +346,7 @@ struct radv_shader_info {
       enum gl_tess_spacing spacing;
       bool ccw;
       bool point_mode;
+      unsigned tcs_vertices_out;
       uint8_t num_linked_inputs;
       uint8_t num_linked_patch_inputs;
       uint8_t num_linked_outputs;
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 8afc134..c242534 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -491,6 +491,7 @@ gather_shader_info_tes(struct radv_device *device, const nir_shader *nir, struct
    info->tes.spacing = nir->info.tess.spacing;
    info->tes.ccw = nir->info.tess.ccw;
    info->tes.point_mode = nir->info.tess.point_mode;
+   info->tes.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
 
    if (!info->outputs_linked)
       info->tes.num_linked_outputs = util_last_bit64(nir->info.outputs_written);