From: Krzysztof Kozlowski Date: Sat, 31 Jul 2021 09:24:06 +0000 (+0200) Subject: ARM: dts: exynos: add CPU topology to Exynos5260 X-Git-Tag: accepted/tizen/unified/20230118.172025~6510^2~19^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=fa0c56dbc3a1b116d280c3a3a97052ea38e4ea2b;p=platform%2Fkernel%2Flinux-rpi.git ARM: dts: exynos: add CPU topology to Exynos5260 Describe Exynos5260 CPU topology. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210731092409.31496-5-krzysztof.kozlowski@canonical.com --- diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 973448c..52fa211 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -34,42 +34,68 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + core1 { + cpu = <&cpu3>; + }; + core2 { + cpu = <&cpu4>; + }; + core3 { + cpu = <&cpu5>; + }; + }; + }; + + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; cci-control-port = <&cci_control1>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; cci-control-port = <&cci_control1>; }; - cpu@100 { + cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; cci-control-port = <&cci_control0>; }; - cpu@101 { + cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; cci-control-port = <&cci_control0>; }; - cpu@102 { + cpu4: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; cci-control-port = <&cci_control0>; }; - cpu@103 { + cpu5: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x103>;