From: Tom Rini <trini@ti.com>
Date: Mon, 24 Jun 2013 20:37:01 +0000 (-0400)
Subject: Merge branch 'master' of git://git.denx.de/u-boot-spi
X-Git-Tag: v2013.07-rc2~59
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f9c1456cf632175afb7d6b27f42f1aab8432be0f;hp=b9e31be0f8adc1a55179ae3b45c9e274f4650007;p=platform%2Fkernel%2Fu-boot.git

Merge branch 'master' of git://git.denx.de/u-boot-spi
---

diff --git a/Makefile b/Makefile
index 693b3f2..fdaddb9 100644
--- a/Makefile
+++ b/Makefile
@@ -743,6 +743,13 @@ tools: $(VERSION_FILE) $(TIMESTAMP_FILE)
 	$(MAKE) -C $@ all
 endif	# config.mk
 
+# ARM relocations should all be R_ARM_RELATIVE.
+checkarmreloc: $(obj)u-boot
+	@if test "R_ARM_RELATIVE" != \
+		"`readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \
+		then echo "$< contains relocations other than \
+		R_ARM_RELATIVE"; false; fi
+
 $(VERSION_FILE):
 		@mkdir -p $(dir $(VERSION_FILE))
 		@( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \
diff --git a/README b/README
index 6db33c4..137e8cb 100644
--- a/README
+++ b/README
@@ -413,11 +413,22 @@ The following options need to be configured:
 		See Freescale App Note 4493 for more information about
 		this erratum.
 
+		CONFIG_A003399_NOR_WORKAROUND
+		Enables a workaround for IFC erratum A003399. It is only
+		requred during NOR boot.
+
 		CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
 
 		This is the value to write into CCSR offset 0x18600
 		according to the A004510 workaround.
 
+		CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
+		This value denotes start offset of M2 memory
+		which is directly connected to the DSP core.
+
+		CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+		This value denotes start offset of DSP CCSR space.
+
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -3027,6 +3038,14 @@ FIT uImage format:
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 
+		CONFIG_SPL_ENV_SUPPORT
+		Support for the environment operating in SPL binary
+
+		CONFIG_SPL_NET_SUPPORT
+		Support for the net/libnet.o in SPL binary.
+		It conflicts with SPL env from storage medium specified by
+		CONFIG_ENV_IS_xxx but CONFIG_ENV_IS_NOWHERE
+
 		CONFIG_SPL_PAD_TO
 		Image offset to which the SPL should be padded before appending
 		the SPL payload. By default, this is defined as
@@ -3969,6 +3988,9 @@ Low Level (hardware related) configuration options:
 - CONFIG_SRIO2:
 		Board has SRIO 2 port available
 
+- CONFIG_SRIO_PCIE_BOOT_MASTER
+		Board can support master function for Boot from SRIO and PCIE
+
 - CONFIG_SYS_SRIOn_MEM_VIRT:
 		Virtual Address of SRIO port 'n' memory region
 
@@ -4079,6 +4101,11 @@ Low Level (hardware related) configuration options:
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.
 
+- CONFIG_SYS_MPC85XX_NO_RESETVEC
+		Only for 85xx systems. If this variable is specified, the section
+		.resetvec is not kept and the section .bootpg is placed in the
+		previous 4k of the .text section.
+
 - CONFIG_ARCH_MAP_SYSMEM
 		Generally U-Boot (and in particular the md command) uses
 		effective address. It is therefore not necessary to regard
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index dc64160..e80e1ed 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -109,3 +109,8 @@ ifeq ($(GAS_BUG_12532),y)
 PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
 endif
 endif
+
+# check that only R_ARM_RELATIVE relocations are generated
+ifneq ($(CONFIG_SPL_BUILD),y)
+ALL-y	+= checkarmreloc
+endif
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
index cf55bf7..367c805 100644
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -31,6 +31,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
+		*(.__image_copy_start)
 	  arch/arm/cpu/arm920t/start.o	(.text*)
 		/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
 	  . = 0x1000;
@@ -56,7 +57,10 @@ SECTIONS
 
 	. = ALIGN(4);
 
-	__image_copy_end = .;
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
 
 	__bss_start = .;
 	.bss : { *(.bss*) }
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index 673c725..f4e7525 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -57,11 +57,6 @@ SECTIONS
 		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
 	.bss : {
 		. = ALIGN(4);
 		__bss_start = .;
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index 967a135..446d095 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -57,11 +57,6 @@ SECTIONS
 		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
 	.bss : {
 		. = ALIGN(4);
 		__bss_start = .;
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 885fb2d..b935a29 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -149,3 +149,43 @@ int arch_misc_init(void)
 #endif
 	return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+void rtc32k_enable(void)
+{
+	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(0x83e70b13, &rtc->kick0r);
+	writel(0x95a4f1e0, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+void uart_soft_reset(void)
+{
+	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+	u32 regval;
+
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_RESET;
+	writel(regval, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regval = readl(&uart_base->uartsyscfg);
+	regval |= UART_SMART_IDLE_EN;
+	writel(regval, &uart_base->uartsyscfg);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index a1efc75..9c4d0b4 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -246,7 +246,7 @@ static void enable_per_clocks(void)
 		;
 }
 
-static void mpu_pll_config(void)
+void mpu_pll_config_val(int mpull_m)
 {
 	u32 clkmode, clksel, div_m2;
 
@@ -260,7 +260,7 @@ static void mpu_pll_config(void)
 		;
 
 	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
+	clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
 	writel(clksel, &cmwkup->clkseldpllmpu);
 
 	div_m2 = div_m2 & ~CLK_DIV_MASK;
@@ -274,6 +274,11 @@ static void mpu_pll_config(void)
 		;
 }
 
+static void mpu_pll_config(void)
+{
+	mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+}
+
 static void core_pll_config(void)
 {
 	u32 clkmode, clksel, div_m4, div_m5, div_m6;
diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile
index 9119961..b2f9152 100644
--- a/arch/arm/cpu/armv7/exynos/Makefile
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	+= clock.o power.o soc.o system.o pinmux.o
+COBJS	+= clock.o power.o soc.o system.o pinmux.o tzpc.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 223660a..e1c4246 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -116,10 +116,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 		/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
 		fout = (m + k / 1024) * (freq / (p * (1 << s)));
 	} else {
-		if (s < 1)
-			s = 1;
-		/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
-		fout = m * (freq / (p * (1 << (s - 1))));
+		/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+		fout = m * (freq / (p * (1 << s)));
 	}
 
 	return fout;
@@ -613,7 +611,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
 		(struct exynos4_clock *)samsung_get_base_clock();
 	unsigned long uclk, sclk;
 	unsigned int sel, ratio, pre_ratio;
-	int shift;
+	int shift = 0;
 
 	sel = readl(&clk->src_fsys);
 	sel = (sel >> (dev_index << 2)) & 0xf;
@@ -662,7 +660,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned long uclk, sclk;
 	unsigned int sel, ratio, pre_ratio;
-	int shift;
+	int shift = 0;
 
 	sel = readl(&clk->src_fsys);
 	sel = (sel >> (dev_index << 2)) & 0xf;
diff --git a/board/samsung/smdk5250/tzpc_init.c b/arch/arm/cpu/armv7/exynos/tzpc.c
similarity index 69%
rename from board/samsung/smdk5250/tzpc_init.c
rename to arch/arm/cpu/armv7/exynos/tzpc.c
index c833541..f5e8e9c 100644
--- a/board/samsung/smdk5250/tzpc_init.c
+++ b/arch/arm/cpu/armv7/exynos/tzpc.c
@@ -22,27 +22,36 @@
  * MA 02111-1307 USA
  */
 
+#include <common.h>
 #include <asm/arch/tzpc.h>
-#include"setup.h"
+#include <asm/io.h>
 
 /* Setting TZPC[TrustZone Protection Controller] */
 void tzpc_init(void)
 {
 	struct exynos_tzpc *tzpc;
-	unsigned int addr;
+	unsigned int addr, start = 0, end = 0;
 
-	for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
+	start = samsung_get_base_tzpc();
+
+	if (cpu_is_exynos5())
+		end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+	else if (cpu_is_exynos4())
+		end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
+
+	for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) {
 		tzpc = (struct exynos_tzpc *)addr;
 
-		if (addr == TZPC0_BASE)
+		if (addr == start)
 			writel(R0SIZE, &tzpc->r0size);
 
 		writel(DECPROTXSET, &tzpc->decprot0set);
 		writel(DECPROTXSET, &tzpc->decprot1set);
 
-		if (addr != TZPC9_BASE) {
-			writel(DECPROTXSET, &tzpc->decprot2set);
-			writel(DECPROTXSET, &tzpc->decprot3set);
-		}
+		if (cpu_is_exynos5() && (addr == end))
+			break;
+
+		writel(DECPROTXSET, &tzpc->decprot2set);
+		writel(DECPROTXSET, &tzpc->decprot3set);
 	}
 }
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile
index 1705399..0c38bd0 100644
--- a/arch/arm/cpu/armv7/s5p-common/Makefile
+++ b/arch/arm/cpu/armv7/s5p-common/Makefile
@@ -26,9 +26,11 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)libs5p-common.o
 
 COBJS-y		+= cpu_info.o
+ifndef CONFIG_SPL_BUILD
 COBJS-y		+= timer.o
 COBJS-y		+= sromc.o
 COBJS-$(CONFIG_PWM)	+= pwm.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
index 553589c..54bafda 100644
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ b/arch/arm/cpu/ixp/u-boot.lds
@@ -31,6 +31,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text :
 	{
+		*(.__image_copy_start)
 		arch/arm/cpu/ixp/start.o(.text*)
 		*(.text*)
 	}
@@ -54,17 +55,23 @@ SECTIONS
 
 	. = ALIGN(4);
 
-	__image_copy_end = .;
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
 
 	.rel.dyn : {
-		__rel_dyn_start = .;
 		*(.rel*)
-		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
 	}
 
 	_end = .;
@@ -88,6 +95,7 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
+	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }
 	/DISCARD/ : { *(.dynamic*) }
 	/DISCARD/ : { *(.plt*) }
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index 1408f03..b6ed25f 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -58,11 +58,6 @@ SECTIONS
 		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
 	_end = .;
 
 	.bss __rel_dyn_start (OVERLAY) : {
@@ -72,6 +67,7 @@ SECTIONS
 		__bss_end = .;
 	}
 
+	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }
 	/DISCARD/ : { *(.dynamic*) }
 	/DISCARD/ : { *(.plt*) }
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index d9bbee3..3037885 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -33,7 +33,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text :
 	{
-		__image_copy_start = .;
+		*(.__image_copy_start)
 		CPUDIR/start.o (.text*)
 		*(.text*)
 	}
@@ -57,17 +57,23 @@ SECTIONS
 
 	. = ALIGN(4);
 
-	__image_copy_end = .;
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
 
 	.rel.dyn : {
-		__rel_dyn_start = .;
 		*(.rel*)
-		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
 	}
 
 	_end = .;
@@ -101,6 +107,7 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
+	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }
 	/DISCARD/ : { *(.dynamic*) }
 	/DISCARD/ : { *(.plt*) }
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index df4b231..cee4fe8 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -169,4 +169,37 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 	};
+
+	mmc@12200000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12200000 0x1000>;
+		interrupts = <0 75 0>;
+	};
+
+	mmc@12210000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12210000 0x1000>;
+		interrupts = <0 76 0>;
+	};
+
+	mmc@12220000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12220000 0x1000>;
+		interrupts = <0 77 0>;
+	};
+
+	mmc@12230000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5250-dwmmc";
+		reg = <0x12230000 0x1000>;
+		interrupts = <0 78 0>;
+	};
+
 };
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index fedc674..307ac28 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -32,6 +32,7 @@ extern struct ctrl_stat *cstat;
 u32 get_device_type(void);
 void save_omap_boot_params(void);
 void setup_clocks_for_console(void);
+void mpu_pll_config_val(int mpull_m);
 void ddr_pll_config(unsigned int ddrpll_M);
 
 void sdelay(unsigned long);
@@ -41,4 +42,7 @@ void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);
 void omap_nand_switch_ecc(uint32_t, uint32_t);
+
+void rtc32k_enable(void);
+void uart_soft_reset(void);
 #endif
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index f76e489..36b98c8 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -38,6 +38,7 @@
 #define EXYNOS4_CLOCK_BASE		0x10030000
 #define EXYNOS4_SYSTIMER_BASE		0x10050000
 #define EXYNOS4_WATCHDOG_BASE		0x10060000
+#define EXYNOS4_TZPC_BASE		0x10110000
 #define EXYNOS4_MIU_BASE		0x10600000
 #define EXYNOS4_DMC0_BASE		0x10400000
 #define EXYNOS4_DMC1_BASE		0x10410000
@@ -74,6 +75,7 @@
 #define EXYNOS4X12_CLOCK_BASE		0x10030000
 #define EXYNOS4X12_SYSTIMER_BASE	0x10050000
 #define EXYNOS4X12_WATCHDOG_BASE	0x10060000
+#define EXYNOS4X12_TZPC_BASE		0x10110000
 #define EXYNOS4X12_DMC0_BASE		0x10600000
 #define EXYNOS4X12_DMC1_BASE		0x10610000
 #define EXYNOS4X12_GPIO_PART4_BASE	0x106E0000
@@ -107,6 +109,7 @@
 #define EXYNOS5_POWER_BASE		0x10040000
 #define EXYNOS5_SWRESET			0x10040400
 #define EXYNOS5_SYSREG_BASE		0x10050000
+#define EXYNOS5_TZPC_BASE		0x10100000
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
 #define EXYNOS5_ACE_SFR_BASE            0x10830000
 #define EXYNOS5_DMC_PHY0_BASE		0x10C00000
@@ -233,6 +236,7 @@ SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
 SAMSUNG_BASE(spi, SPI_BASE)
 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+SAMSUNG_BASE(tzpc, TZPC_BASE)
 #endif
 
 #endif	/* _EXYNOS4_CPU_H */
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
index 8acdf9b..3b147b8 100644
--- a/arch/arm/include/asm/arch-exynos/dwmmc.h
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -27,10 +27,7 @@
 #define DWMCI_SET_DRV_CLK(x)	((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)	((x) << 24)
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index);
-
-static inline unsigned int exynos_dwmmc_init(int index, int bus_width)
-{
-	unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-	return exynos_dwmci_init(base, bus_width, index);
-}
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob);
+#endif
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel);
diff --git a/arch/arm/include/asm/arch-exynos/tmu.h b/arch/arm/include/asm/arch-exynos/tmu.h
index 7e0158e..cad3569 100644
--- a/arch/arm/include/asm/arch-exynos/tmu.h
+++ b/arch/arm/include/asm/arch-exynos/tmu.h
@@ -21,38 +21,30 @@
 #define __ASM_ARCH_TMU_H
 
 struct exynos5_tmu_reg {
-	unsigned triminfo;
-	unsigned rsvd1;
-	unsigned rsvd2;
-	unsigned rsvd3;
-	unsigned rsvd4;
-	unsigned triminfo_control;
-	unsigned rsvd5;
-	unsigned rsvd6;
-	unsigned tmu_control;
-	unsigned rsvd7;
-	unsigned tmu_status;
-	unsigned sampling_internal;
-	unsigned counter_value0;
-	unsigned counter_value1;
-	unsigned rsvd8;
-	unsigned rsvd9;
-	unsigned current_temp;
-	unsigned rsvd10;
-	unsigned rsvd11;
-	unsigned rsvd12;
-	unsigned threshold_temp_rise;
-	unsigned threshold_temp_fall;
-	unsigned rsvd13;
-	unsigned rsvd14;
-	unsigned past_temp3_0;
-	unsigned past_temp7_4;
-	unsigned past_temp11_8;
-	unsigned past_temp15_12;
-	unsigned inten;
-	unsigned intstat;
-	unsigned intclear;
-	unsigned rsvd15;
-	unsigned emul_con;
+	u32 triminfo;
+	u32 rsvd1[4];
+	u32 triminfo_control;
+	u32 rsvd5[2];
+	u32 tmu_control;
+	u32 rsvd7;
+	u32 tmu_status;
+	u32 sampling_internal;
+	u32 counter_value0;
+	u32 counter_value1;
+	u32 rsvd8[2];
+	u32 current_temp;
+	u32 rsvd10[3];
+	u32 threshold_temp_rise;
+	u32 threshold_temp_fall;
+	u32 rsvd13[2];
+	u32 past_temp3_0;
+	u32 past_temp7_4;
+	u32 past_temp11_8;
+	u32 past_temp15_12;
+	u32 inten;
+	u32 intstat;
+	u32 intclear;
+	u32 rsvd15;
+	u32 emul_con;
 };
 #endif /* __ASM_ARCH_TMU_H */
diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h
index c5eb4b1..4d9c3a3 100644
--- a/arch/arm/include/asm/arch-exynos/tzpc.h
+++ b/arch/arm/include/asm/arch-exynos/tzpc.h
@@ -47,6 +47,26 @@ struct exynos_tzpc {
 	unsigned int pcellid2;
 	unsigned int pcellid3;
 };
+
+#define EXYNOS4_NR_TZPC_BANKS		6
+#define EXYNOS5_NR_TZPC_BANKS		10
+
+/* TZPC : Register Offsets */
+#define TZPC_BASE_OFFSET		0x10000
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE			0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET		0xFF
+void tzpc_init(void);
+
 #endif
 
 #endif
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 8ad9f66..9ecafb2 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -43,7 +43,7 @@ SOBJS-y += relocate.o
 ifndef CONFIG_SYS_GENERIC_BOARD
 COBJS-y	+= board.o
 endif
-COBJS-y += bss.o
+COBJS-y += sections.o
 
 COBJS-y	+= bootm.o
 COBJS-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 4446da9..949b9e8 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -37,56 +37,34 @@
  */
 
 ENTRY(relocate_code)
-	mov	r6, r0	/* save addr of destination */
-
-	ldr	r0, =_start		/* r0 <- SRC &_start */
-	subs	r9, r6, r0		/* r9 <- relocation offset */
+	ldr	r1, =__image_copy_start	/* r1 <- SRC &__image_copy_start */
+	subs	r9, r0, r1		/* r9 <- relocation offset */
 	beq	relocate_done		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy loop */
-	adr	r7, relocate_code	/* r7 <- SRC &relocate_code */
-	ldr	r3, _image_copy_end_ofs	/* r3 <- __image_copy_end local ofs */
-	add	r2, r7, r3		/* r2 <- SRC &__image_copy_end */
+	ldr	r2, =__image_copy_end	/* r2 <- SRC &__image_copy_end */
 
 copy_loop:
-	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
-	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
+	ldmia	r1!, {r10-r11}		/* copy from source address [r1]    */
+	stmia	r0!, {r10-r11}		/* copy to   target address [r0]    */
+	cmp	r1, r2			/* until source end address [r2]    */
 	blo	copy_loop
 
 	/*
 	 * fix .rel.dyn relocations
 	 */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- __dynsym_start local ofs */
-	add	r10, r10, r7		/* r10 <- SRC &__dynsym_start */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- __rel_dyn_start local ofs */
-	add	r2, r2, r7		/* r2 <- SRC &__rel_dyn_start */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- __rel_dyn_end local ofs */
-	add	r3, r3, r7		/* r3 <- SRC &__rel_dyn_end */
+	ldr	r2, =__rel_dyn_start	/* r2 <- SRC &__rel_dyn_start */
+	ldr	r3, =__rel_dyn_end	/* r3 <- SRC &__rel_dyn_end */
 fixloop:
-	ldr	r0, [r2]		/* r0 <- SRC location to fix up */
-	add	r0, r0, r9		/* r0 <- DST location to fix up */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
+	ldmia	r2!, {r0-r1}		/* (r0,r1) <- (SRC location,fixup) */
+	and	r1, r1, #0xff
+	cmp	r1, #23			/* relative fixup? */
+	bne	fixnext
+
 	/* relative fix: increase location by offset */
+	add	r0, r0, r9
 	ldr	r1, [r0]
 	add	r1, r1, r9
-fixnext:
 	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
+fixnext:
 	cmp	r2, r3
 	blo	fixloop
 
@@ -100,13 +78,4 @@ relocate_done:
         bx        lr
 #endif
 
-_image_copy_end_ofs:
-	.word __image_copy_end - relocate_code
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - relocate_code
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - relocate_code
-_dynsym_start_ofs:
-	.word __dynsym_start - relocate_code
-
 ENDPROC(relocate_code)
diff --git a/arch/arm/lib/bss.c b/arch/arm/lib/sections.c
similarity index 79%
rename from arch/arm/lib/bss.c
rename to arch/arm/lib/sections.c
index 99eda59..5921dd8 100644
--- a/arch/arm/lib/bss.c
+++ b/arch/arm/lib/sections.c
@@ -35,5 +35,9 @@
  * aliasing warnings.
  */
 
-char __bss_start[0] __attribute__((used, section(".__bss_start")));
-char __bss_end[0] __attribute__((used, section(".__bss_end")));
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
+char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 2318064..4669883 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -73,6 +73,7 @@ COBJS-$(CONFIG_P1014)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1020)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1021)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1022)	+= ddr-gen3.o
+COBJS-$(CONFIG_P1023)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1024)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1025)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2010)	+= ddr-gen3.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 422782c..a7ed877 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -258,6 +258,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
 	puts("Work-around for Erratum USB14 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
+	puts("Work-around for Erratum A006593 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 6ce483e..fbee753 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -121,16 +121,16 @@ int checkcpu (void)
 	switch(ver) {
 	case PVR_VER_E500_V1:
 	case PVR_VER_E500_V2:
-		puts("E500");
+		puts("e500");
 		break;
 	case PVR_VER_E500MC:
-		puts("E500MC");
+		puts("e500mc");
 		break;
 	case PVR_VER_E5500:
-		puts("E5500");
+		puts("e5500");
 		break;
 	case PVR_VER_E6500:
-		puts("E6500");
+		puts("e6500");
 		break;
 	default:
 		puts("Unknown");
@@ -341,7 +341,7 @@ phys_size_t initdram(int board_type)
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
 	return fsl_ddr_sdram_size();
 #else
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 #endif
 }
 #else /* CONFIG_SYS_RAMBOOT */
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4067f05..3c8f59c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -172,6 +172,9 @@ static void enable_cpc(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
 		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
+		setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
+#endif
 
 		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 		/* Read back to sync write */
@@ -564,7 +567,7 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
 	srio_init();
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	char *s = getenv("bootmaster");
 	if (s) {
 		if (!strcmp(s, "SRIO1")) {
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 234fde4..837c034 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -25,7 +25,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_A003399_NOR_WORKAROUND
 void setup_ifc(void)
 {
 	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
@@ -99,7 +99,7 @@ void cpu_init_early_f(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
-#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_A003399_NOR_WORKAROUND
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	u32  *dst, *src;
 	void (*setup_ifc_sram)(void);
@@ -138,7 +138,7 @@ void cpu_init_early_f(void)
  * Work Around for IFC Erratum A003399, issue will hit only when execution
  * from NOR Flash
  */
-#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_A003399_NOR_WORKAROUND
 #define SRAM_BASE_ADDR	(0x00000000)
 	/* TLB for SRAM */
 	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
@@ -180,5 +180,9 @@ void cpu_init_early_f(void)
 
 	invalidate_tlb(1);
 
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL)
+	disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
+#endif
+
 	init_tlbs();
 }
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 288f7b2..bb95f3d 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -663,7 +663,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_FSL_CORENET
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
 		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
-	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2",
+	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
 		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 	do_fixup_by_compat_u32(blob, "fsl,mpic",
 		"clock-frequency", get_bus_freq(0)/2, 1);
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
index 6dadeb8..ec96e81 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c
@@ -228,7 +228,7 @@ void fsl_serdes_init(void)
 		break;
 	}
 
-	if (srds1_io_sel > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds1_io_sel >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
 		return;
 	}
@@ -237,7 +237,7 @@ void fsl_serdes_init(void)
 		serdes1_prtcl_map |= (1 << lane_prtcl);
 	}
 
-	if (srds2_io_sel > ARRAY_SIZE(serdes2_cfg_tbl)) {
+	if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) {
 		printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
index 7c49097..3483366 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c
@@ -68,7 +68,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
@@ -77,7 +77,7 @@ void fsl_serdes_init(void)
 		serdes1_prtcl_map |= (1 << lane_prtcl);
 	}
 
-	if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
index 76288cd..c9eea15 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
@@ -53,7 +53,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
 
-	if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
 		return ;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
index 2582637..49a0290 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c
@@ -53,7 +53,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
index f480c26..7af6aff 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c
@@ -62,7 +62,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
index 2ff5d9a..fcccb52 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c
@@ -57,7 +57,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
index e8a0387..1f7dba0 100644
--- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c
@@ -54,7 +54,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
@@ -63,7 +63,7 @@ void fsl_serdes_init(void)
 		serdes1_prtcl_map |= (1 << lane_prtcl);
 	}
 
-	if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
index 1849c16..d6d2696 100644
--- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c
@@ -73,7 +73,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
index e4c9c22..ed49920 100644
--- a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c
@@ -93,7 +93,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
@@ -102,7 +102,7 @@ void fsl_serdes_init(void)
 		serdes1_prtcl_map |= (1 << lane_prtcl);
 	}
 
-	if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
index c8ab5d6..0b4ae90 100644
--- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c
@@ -41,7 +41,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
index 389ff6b..01af333 100644
--- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c
@@ -61,7 +61,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
index eec4ffe..87335c9 100644
--- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
@@ -90,7 +90,7 @@ int is_serdes_prtcl_valid(u32 prtcl)
 	u32 svr = get_svr();
 	u32 ver = SVR_SOC_VER(svr);
 
-	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
 
 	/* P2040[e] does not support XAUI */
diff --git a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
index fba9ff2..a36dcd5 100644
--- a/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p3041_serdes.c
@@ -139,7 +139,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
 int is_serdes_prtcl_valid(u32 prtcl) {
 	int i;
 
-	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
 
 	for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
index 87bd795..94ec445 100644
--- a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
@@ -86,7 +86,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
 int is_serdes_prtcl_valid(u32 prtcl) {
 	int i;
 
-	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
 
 	for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c
index fba9ff2..a36dcd5 100644
--- a/arch/powerpc/cpu/mpc85xx/p5020_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p5020_serdes.c
@@ -139,7 +139,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
 int is_serdes_prtcl_valid(u32 prtcl) {
 	int i;
 
-	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
 
 	for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
index 890b88e..d646e85 100644
--- a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
@@ -105,7 +105,7 @@ int is_serdes_prtcl_valid(u32 prtcl)
 {
 	int i;
 
-	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
 
 	for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 4f0480b..2657982 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1795,7 +1795,7 @@ clear_bss:
 	stw	r0,0(r3)
 	addi	r3,r3,4
 	cmplw	0,r3,r4
-	bne	5b
+	blt	5b
 6:
 
 	mr	r3,r9		/* Init Data pointer		*/
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
index 8261e03..19add9f 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_serdes.c
@@ -81,7 +81,7 @@ int is_serdes_prtcl_valid(int serdes, u32 prtcl)
 {
 	int i;
 
-	if (prtcl > (ARRAY_SIZE(serdes_cfg_tbl[serdes])))
+	if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes]))
 		return 0;
 
 	for (i = 0; i < SRDS_MAX_LANES; i++) {
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index f2b7bff..20284ed 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -26,6 +26,13 @@
 #include "config.h"	/* CONFIG_BOARDDIR */
 
 OUTPUT_ARCH(powerpc)
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+PHDRS
+{
+	text PT_LOAD;
+	bss PT_LOAD;
+}
+#endif
 SECTIONS
 {
 	. = CONFIG_SPL_TEXT_BASE;
@@ -60,7 +67,7 @@ SECTIONS
 #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
 	.bootpg ADDR(.text) + 0x1000 :
 	{
-		start.o	(.bootpg)
+		arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
 	}
 #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
 #elif defined(CONFIG_FSL_ELBC)
@@ -68,9 +75,16 @@ SECTIONS
 #else
 #error unknown NAND controller
 #endif
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+	.bootpg ADDR(.text) - 0x1000 :
+	{
+		KEEP(*(.bootpg))
+	} :text = 0xffff
+#else
 	.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
 		KEEP(*(.resetvec))
 	} = 0xffff
+#endif
 
 	/*
 	 * Make sure that the bss segment isn't linked at 0x0, otherwise its
@@ -78,10 +92,12 @@ SECTIONS
 	 */
 	. |= 0x10;
 
+	. = ALIGN(4);
 	__bss_start = .;
 	.bss : {
 		*(.sbss*)
 		*(.bss*)
 	}
+	. = ALIGN(4);
 	__bss_end = .;
 }
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 0503dce..2643563 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -95,6 +95,13 @@ SECTIONS
   . = ALIGN(256);
   __init_end = .;
 
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+  .bootpg ADDR(.text) - 0x1000 :
+  {
+    KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
+  } :text = 0xffff
+  . = ADDR(.text) + 0x80000;
+#else
   .bootpg RESET_VECTOR_ADDRESS - 0xffc :
   {
     arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
@@ -117,6 +124,7 @@ SECTIONS
 #if (RESET_VECTOR_ADDRESS == 0xfffffffc)
   . |= 0x10;
 #endif
+#endif
 
   __bss_start = .;
   .bss (NOLOAD)       :
diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c
index c553415..5ed3eb2 100644
--- a/arch/powerpc/cpu/mpc86xx/cpu.c
+++ b/arch/powerpc/cpu/mpc86xx/cpu.c
@@ -78,7 +78,7 @@ checkcpu(void)
 	major = PVR_E600_MAJ(pvr);
 	minor = PVR_E600_MIN(pvr);
 
-	printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
+	printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
 	if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
 		puts("\n    Core1Translation Enabled");
 	debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
diff --git a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
index 0dc1975..0342e34 100644
--- a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
+++ b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c
@@ -64,7 +64,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
@@ -73,7 +73,7 @@ void fsl_serdes_init(void)
 		serdes1_prtcl_map |= (1 << lane_prtcl);
 	}
 
-	if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
index 3ae9069..21c5ddb 100644
--- a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
+++ b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c
@@ -73,7 +73,7 @@ void fsl_serdes_init(void)
 
 	debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
 
-	if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
@@ -82,7 +82,7 @@ void fsl_serdes_init(void)
 		serdes1_prtcl_map |= (1 << lane_prtcl);
 	}
 
-	if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
+	if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
 		return;
 	}
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
index 56b319f..4e8a441 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -26,7 +26,7 @@ void print_ifc_regs(void)
 	int i, j;
 
 	printf("IFC Controller Registers\n");
-	for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
+	for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
 		printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
 			i, get_ifc_cspr(i), i, get_ifc_amask(i),
 			i, get_ifc_csor(i));
@@ -43,7 +43,7 @@ void init_early_memctl_regs(void)
 	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
 	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
 
-#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT)
+#ifndef CONFIG_A003399_NOR_WORKAROUND
 #ifdef CONFIG_SYS_CSPR0_EXT
 	set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
 #endif
@@ -94,4 +94,60 @@ void init_early_memctl_regs(void)
 	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
 	set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
 #endif
+
+#ifdef CONFIG_SYS_CSPR4_EXT
+	set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+	set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+
+	set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
+	set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
+	set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#endif
+
+#ifdef CONFIG_SYS_CSPR5_EXT
+	set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+	set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
+
+	set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
+	set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
+	set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#endif
+
+#ifdef CONFIG_SYS_CSPR6_EXT
+	set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+	set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+
+	set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
+	set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
+	set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#endif
+
+#ifdef CONFIG_SYS_CSPR7_EXT
+	set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+	set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+
+	set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
+	set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
+	set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+#endif
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 6e6f7dc..90d1065 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -24,7 +24,7 @@
 #include <asm/fsl_srio.h>
 #include <asm/errno.h>
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 #define SRIO_PORT_ACCEPT_ALL 0x10000001
 #define SRIO_IB_ATMU_AR 0x80f55000
 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -299,7 +299,7 @@ void srio_init(void)
 	}
 }
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 void srio_boot_master(int port)
 {
 	struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 1009a31..1d46b14 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -139,6 +139,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -337,7 +338,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -371,7 +371,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -413,7 +412,6 @@
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -449,7 +447,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -494,6 +491,9 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -506,6 +506,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -541,6 +542,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		2
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
@@ -553,6 +555,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004468
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 
@@ -566,6 +569,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
@@ -573,6 +577,7 @@
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 #define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
 #ifdef CONFIG_PPC_B4860
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index ba41b73..3baf4cc 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -21,6 +21,7 @@
 #ifndef __ASM_PPC_FSL_IFC_H
 #define __ASM_PPC_FSL_IFC_H
 
+#ifdef CONFIG_FSL_IFC
 #include <config.h>
 #include <common.h>
 
@@ -798,13 +799,15 @@ extern void init_early_memctl_regs(void);
 #define set_ifc_ftim(i, j, v) \
 			(out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
 
-#define FSL_IFC_BANK_COUNT	4
-
 enum ifc_chip_sel {
 	IFC_CS0,
 	IFC_CS1,
 	IFC_CS2,
 	IFC_CS3,
+	IFC_CS4,
+	IFC_CS5,
+	IFC_CS6,
+	IFC_CS7,
 };
 
 enum ifc_ftims {
@@ -907,6 +910,49 @@ struct fsl_ifc_gpcm {
 	u32 res4[0x1F3];
 };
 
+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define IFC_CSPR_REG_LEN	148
+#define IFC_AMASK_REG_LEN	144
+#define IFC_CSOR_REG_LEN	144
+#define IFC_FTIM_REG_LEN	576
+
+#define IFC_CSPR_USED_LEN	sizeof(struct fsl_ifc_cspr) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_AMASK_USED_LEN	sizeof(struct fsl_ifc_amask) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_CSOR_USED_LEN	sizeof(struct fsl_ifc_csor) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_FTIM_USED_LEN	sizeof(struct fsl_ifc_ftim) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif
+
+struct fsl_ifc_cspr {
+	u32 cspr_ext;
+	u32 cspr;
+	u32 res;
+};
+
+struct fsl_ifc_amask {
+	u32 amask;
+	u32 res[0x2];
+};
+
+struct fsl_ifc_csor {
+	u32 csor;
+	u32 csor_ext;
+	u32 res;
+};
+
+struct fsl_ifc_ftim {
+	u32 ftim[4];
+	u32 res[0x8];
+};
 
 /*
  * IFC Controller Registers
@@ -914,44 +960,30 @@ struct fsl_ifc_gpcm {
 struct fsl_ifc {
 	u32 ifc_rev;
 	u32 res1[0x2];
-	struct {
-		u32 cspr_ext;
-		u32 cspr;
-		u32 res2;
-	} cspr_cs[FSL_IFC_BANK_COUNT];
-	u32 res3[0x19];
-	struct {
-		u32 amask;
-		u32 res4[0x2];
-	} amask_cs[FSL_IFC_BANK_COUNT];
-	u32 res5[0x17];
-	struct {
-		u32 csor_ext;
-		u32 csor;
-		u32 res6;
-	} csor_cs[FSL_IFC_BANK_COUNT];
-	u32 res7[0x19];
-	struct {
-		u32 ftim[4];
-		u32 res8[0x8];
-	} ftim_cs[FSL_IFC_BANK_COUNT];
-	u32 res9[0x60];
+	struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
+	struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
+	struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
+	struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
 	u32 rb_stat;
-	u32 res10[0x2];
+	u32 res6[0x2];
 	u32 ifc_gcr;
-	u32 res11[0x2];
+	u32 res7[0x2];
 	u32 cm_evter_stat;
-	u32 res12[0x2];
+	u32 res8[0x2];
 	u32 cm_evter_en;
-	u32 res13[0x2];
+	u32 res9[0x2];
 	u32 cm_evter_intr_en;
-	u32 res14[0x2];
+	u32 res10[0x2];
 	u32 cm_erattr0;
 	u32 cm_erattr1;
-	u32 res15[0x2];
+	u32 res11[0x2];
 	u32 ifc_ccr;
 	u32 ifc_csr;
-	u32 res16[0x2EB];
+	u32 res12[0x2EB];
 	struct fsl_ifc_nand ifc_nand;
 	struct fsl_ifc_nor ifc_nor;
 	struct fsl_ifc_gpcm ifc_gpcm;
@@ -961,6 +993,7 @@ struct fsl_ifc {
 #undef CSPR_MSEL_NOR
 #define CSPR_MSEL_NOR	CSPR_MSEL_GPCM
 #endif
+#endif /* CONFIG_FSL_IFC */
 
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_PPC_FSL_IFC_H */
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index 90b264d..bea1636 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -82,11 +82,16 @@ enum law_trgt_if {
 #ifndef CONFIG_MPC8641
 	LAW_TRGT_IF_PCIE_1 = 0x02,
 #endif
+#if defined(CONFIG_BSC9131)
+	LAW_TRGT_IF_OCN_DSP = 0x03,
+#else
 #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
 	LAW_TRGT_IF_PCIE_3 = 0x03,
 #endif
+#endif
 	LAW_TRGT_IF_LBC = 0x04,
 	LAW_TRGT_IF_CCSR = 0x08,
+	LAW_TRGT_IF_DSP_CCSR = 0x09,
 	LAW_TRGT_IF_DDR_INTRLV = 0x0b,
 	LAW_TRGT_IF_RIO = 0x0c,
 	LAW_TRGT_IF_RIO_2 = 0x0d,
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 4052037..db70d04 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1839,11 +1839,13 @@ typedef struct ccsr_gur {
 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT	11
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL		0x000000f8
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT	3
+#define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xfe000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	25
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
+#define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #elif defined(CONFIG_PPC_T1040)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
@@ -2160,7 +2162,7 @@ typedef struct ccsr_gur {
 	u32	porbmsr;	/* POR boot mode status */
 #define MPC85xx_PORBMSR_HA		0x00070000
 #define MPC85xx_PORBMSR_HA_SHIFT	16
-#define MPC85XX_PORBMSR_ROMLOC_SHIFT	24
+#define MPC85xx_PORBMSR_ROMLOC_SHIFT	24
 #define PORBMSR_ROMLOC_SPI	0x6
 #define PORBMSR_ROMLOC_SDHC	0x7
 #define PORBMSR_ROMLOC_NAND_2K	0x9
diff --git a/board/LaCie/common/cpld-gpio-bus.c b/board/LaCie/common/cpld-gpio-bus.c
new file mode 100644
index 0000000..fb9bf8d
--- /dev/null
+++ b/board/LaCie/common/cpld-gpio-bus.c
@@ -0,0 +1,50 @@
+/*
+ * cpld-gpio-bus.c: provides support for the CPLD GPIO bus found on some LaCie
+ * boards (as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO
+ * bus exposes two registers (address and data). Each of this register is made
+ * up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD that
+ * the registers have been updated.
+ *
+ * Mostly this bus is used to configure the LEDs on LaCie boards.
+ *
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <asm/arch/gpio.h>
+#include "cpld-gpio-bus.h"
+
+static void cpld_gpio_bus_set_addr(struct cpld_gpio_bus *bus, unsigned addr)
+{
+	int pin;
+
+	for (pin = 0; pin < bus->num_addr; pin++)
+		kw_gpio_set_value(bus->addr[pin], (addr >> pin) & 1);
+}
+
+static void cpld_gpio_bus_set_data(struct cpld_gpio_bus *bus, unsigned data)
+{
+	int pin;
+
+	for (pin = 0; pin < bus->num_data; pin++)
+		kw_gpio_set_value(bus->data[pin], (data >> pin) & 1);
+}
+
+static void cpld_gpio_bus_enable_select(struct cpld_gpio_bus *bus)
+{
+	/* The transfer is enabled on the raising edge. */
+	kw_gpio_set_value(bus->enable, 0);
+	kw_gpio_set_value(bus->enable, 1);
+}
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *bus,
+			 unsigned addr, unsigned value)
+{
+	cpld_gpio_bus_set_addr(bus, addr);
+	cpld_gpio_bus_set_data(bus, value);
+	cpld_gpio_bus_enable_select(bus);
+}
diff --git a/board/LaCie/common/cpld-gpio-bus.h b/board/LaCie/common/cpld-gpio-bus.h
new file mode 100644
index 0000000..e9e9b96
--- /dev/null
+++ b/board/LaCie/common/cpld-gpio-bus.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _LACIE_CPLD_GPI0_BUS_H
+#define _LACIE_CPLD_GPI0_BUS_H
+
+struct cpld_gpio_bus {
+	unsigned *addr;
+	unsigned num_addr;
+	unsigned *data;
+	unsigned num_data;
+	unsigned enable;
+};
+
+void cpld_gpio_bus_write(struct cpld_gpio_bus *cpld_gpio_bus,
+			 unsigned addr, unsigned value);
+
+#endif /* _LACIE_CPLD_GPI0_BUS_H */
diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile
index fbae48e..9a6dfb6 100644
--- a/board/LaCie/net2big_v2/Makefile
+++ b/board/LaCie/net2big_v2/Makefile
@@ -28,6 +28,9 @@ endif
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o ../common/common.o
+ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
+COBJS	+= ../common/cpld-gpio-bus.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
index e524f35..b133f7c 100644
--- a/board/LaCie/net2big_v2/net2big_v2.c
+++ b/board/LaCie/net2big_v2/net2big_v2.c
@@ -22,6 +22,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <i2c.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
@@ -29,6 +30,7 @@
 
 #include "net2big_v2.h"
 #include "../common/common.h"
+#include "../common/cpld-gpio-bus.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -60,18 +62,18 @@ int board_early_init_f(void)
 		MPP24_GPIO,		/* USB mode select */
 		MPP26_GPIO,		/* USB device vbus */
 		MPP28_GPIO,		/* USB enable host vbus */
-		MPP29_GPIO,		/* GPIO extension ALE */
+		MPP29_GPIO,		/* CPLD GPIO bus ALE */
 		MPP34_GPIO,		/* Rear Push button 0=on 1=off */
 		MPP35_GPIO,		/* Inhibit switch power-off */
 		MPP36_GPIO,		/* SATA HDD1 presence */
 		MPP37_GPIO,		/* SATA HDD2 presence */
 		MPP40_GPIO,		/* eSATA presence */
-		MPP44_GPIO,		/* GPIO extension (data 0) */
-		MPP45_GPIO,		/* GPIO extension (data 1) */
-		MPP46_GPIO,		/* GPIO extension (data 2) */
-		MPP47_GPIO,		/* GPIO extension (addr 0) */
-		MPP48_GPIO,		/* GPIO extension (addr 1) */
-		MPP49_GPIO,		/* GPIO extension (addr 2) */
+		MPP44_GPIO,		/* CPLD GPIO bus (data 0) */
+		MPP45_GPIO,		/* CPLD GPIO bus (data 1) */
+		MPP46_GPIO,		/* CPLD GPIO bus (data 2) */
+		MPP47_GPIO,		/* CPLD GPIO bus (addr 0) */
+		MPP48_GPIO,		/* CPLD GPIO bus (addr 1) */
+		MPP49_GPIO,		/* CPLD GPIO bus (addr 2) */
 		0
 	};
 
@@ -92,8 +94,142 @@ int board_init(void)
 }
 
 #if defined(CONFIG_MISC_INIT_R)
+
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR)
+/*
+ * Start I2C fan (GMT G762 controller)
+ */
+static void init_fan(void)
+{
+	u8 data;
+
+	i2c_set_bus_num(0);
+
+	/* Enable open-loop and PWM modes */
+	data = 0x20;
+	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+		      G762_REG_FAN_CMD1, 1, &data, 1) != 0)
+		goto err;
+	data = 0;
+	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+		      G762_REG_SET_CNT, 1, &data, 1) != 0)
+		goto err;
+	/*
+	 * RPM to PWM (set_out register) fan speed conversion array:
+	 * 0    0x00
+	 * 1500	0x04
+	 * 2800	0x08
+	 * 3400	0x0C
+	 * 3700	0x10
+	 * 4400	0x20
+	 * 4700	0x30
+	 * 4800	0x50
+	 * 5200	0x80
+	 * 5400	0xC0
+	 * 5500	0xFF
+	 *
+	 * Start fan at low speed (2800 RPM):
+	 */
+	data = 0x08;
+	if (i2c_write(CONFIG_SYS_I2C_G762_ADDR,
+		      G762_REG_SET_OUT, 1, &data, 1) != 0)
+		goto err;
+
+	return;
+err:
+	printf("Error: failed to start I2C fan @%02x\n",
+	       CONFIG_SYS_I2C_G762_ADDR);
+}
+#else
+static void init_fan(void) {}
+#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */
+
+#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
+/*
+ * CPLD GPIO bus:
+ *
+ * - address register : bit [0-2] -> GPIO [47-49]
+ * - data register    : bit [0-2] -> GPIO [44-46]
+ * - enable register  : GPIO 29
+ */
+static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
+static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
+
+static struct cpld_gpio_bus cpld_gpio_bus = {
+	.addr		= cpld_gpio_bus_addr,
+	.num_addr	= ARRAY_SIZE(cpld_gpio_bus_addr),
+	.data		= cpld_gpio_bus_data,
+	.num_data	= ARRAY_SIZE(cpld_gpio_bus_data),
+	.enable		= 29,
+};
+
+/*
+ * LEDs configuration:
+ *
+ * The LEDs are controlled by a CPLD and can be configured through
+ * the CPLD GPIO bus.
+ *
+ * Address register selection:
+ *
+ * addr | register
+ * ----------------------------
+ *   0  | front LED
+ *   1  | front LED brightness
+ *   2  | SATA LED brightness
+ *   3  | SATA0 LED
+ *   4  | SATA1 LED
+ *   5  | SATA2 LED
+ *   6  | SATA3 LED
+ *   7  | SATA4 LED
+ *
+ * Data register configuration:
+ *
+ * data | LED brightness
+ * -------------------------------------------------
+ *   0  | min (off)
+ *   -  | -
+ *   7  | max
+ *
+ * data | front LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | fix blue on
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | blink blue on=0.5 sec and blue off=2.5 sec
+ *
+ * data | SATA LED mode
+ * -------------------------------------------------
+ *   0  | fix off
+ *   1  | SATA activity blink
+ *   2  | fix red on
+ *   3  | blink blue on=1 sec and blue off=1 sec
+ *   4  | blink red on=1 sec and red off=1 sec
+ *   5  | blink blue on=2.5 sec and red on=0.5 sec
+ *   6  | blink blue on=1 sec and red on=1 sec
+ *   7  | fix blue on
+ */
+static void init_leds(void)
+{
+	/* Enable the front blue LED */
+	cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
+	cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
+
+	/* Configure SATA LEDs to blink in relation with the SATA activity */
+	cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
+	cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
+	cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
+}
+#else
+static void init_leds(void) {}
+#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
+
 int misc_init_r(void)
 {
+	init_fan();
 #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
 	if (!getenv("ethaddr")) {
 		uchar mac[6];
@@ -101,9 +237,11 @@ int misc_init_r(void)
 			eth_setenv_enetaddr("ethaddr", mac);
 	}
 #endif
+	init_leds();
+
 	return 0;
 }
-#endif
+#endif /* CONFIG_MISC_INIT_R */
 
 #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
 /* Configure and initialize PHY */
diff --git a/board/LaCie/net2big_v2/net2big_v2.h b/board/LaCie/net2big_v2/net2big_v2.h
index f9778f4..83537d6 100644
--- a/board/LaCie/net2big_v2/net2big_v2.h
+++ b/board/LaCie/net2big_v2/net2big_v2.h
@@ -32,4 +32,9 @@
 /* Buttons */
 #define NET2BIG_V2_GPIO_PUSH_BUTTON	34
 
+/* GMT G762 registers (I2C fan controller) */
+#define G762_REG_SET_CNT		0x00
+#define G762_REG_SET_OUT		0x03
+#define G762_REG_FAN_CMD1		0x04
+
 #endif /* NET2BIG_V2_H */
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
index ef4a25b..74aec5f 100644
--- a/board/actux1/u-boot.lds
+++ b/board/actux1/u-boot.lds
@@ -30,6 +30,7 @@ SECTIONS
 
 	. = ALIGN (4);
 	.text : {
+		*(.__image_copy_start)
 		arch/arm/cpu/ixp/start.o(.text*)
 		net/libnet.o(.text*)
 		board/actux1/libactux1.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
 	. = ALIGN (4);
 
-	__image_copy_end = .;
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
 
 	.rel.dyn : {
-		__rel_dyn_start = .;
 		*(.rel*)
-		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
 	}
 
 	_end = .;
@@ -96,6 +103,7 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
+	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }
 	/DISCARD/ : { *(.dynamic*) }
 	/DISCARD/ : { *(.plt*) }
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
index 00ad8b7..c276501 100644
--- a/board/actux2/u-boot.lds
+++ b/board/actux2/u-boot.lds
@@ -30,6 +30,7 @@ SECTIONS
 
 	. = ALIGN (4);
 	.text : {
+		*(.__image_copy_start)
 		arch/arm/cpu/ixp/start.o(.text*)
 		net/libnet.o(.text*)
 		board/actux2/libactux2.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
 	. = ALIGN (4);
 
-	__image_copy_end = .;
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
 
 	.rel.dyn : {
-		__rel_dyn_start = .;
 		*(.rel*)
-		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
 	}
 
 	_end = .;
@@ -96,6 +103,7 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
+	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }
 	/DISCARD/ : { *(.dynamic*) }
 	/DISCARD/ : { *(.plt*) }
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
index 44b990e..5610644 100644
--- a/board/actux3/u-boot.lds
+++ b/board/actux3/u-boot.lds
@@ -30,6 +30,7 @@ SECTIONS
 
 	. = ALIGN (4);
 	.text : {
+		*(.__image_copy_start)
 		arch/arm/cpu/ixp/start.o(.text*)
 		net/libnet.o(.text*)
 		board/actux3/libactux3.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
 	. = ALIGN (4);
 
-	__image_copy_end = .;
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
 
 	.rel.dyn : {
-		__rel_dyn_start = .;
 		*(.rel*)
-		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
 	}
 
 	_end = .;
@@ -96,6 +103,7 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
+	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }
 	/DISCARD/ : { *(.dynamic*) }
 	/DISCARD/ : { *(.plt*) }
diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds
index 1daa1b3..3972685 100644
--- a/board/ait/cam_enc_4xx/u-boot-spl.lds
+++ b/board/ait/cam_enc_4xx/u-boot-spl.lds
@@ -54,11 +54,6 @@ SECTIONS
 		__rel_dyn_end = .;
 	} >.sram
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	} >.sram
-
 	.bss :
 	{
 		. = ALIGN(4);
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index b1b8701..6fa4509 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -55,11 +55,6 @@ SECTIONS
 		__rel_dyn_end = .;
 	} >.sram
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	} >.sram
-
 	.bss :
 	{
 		. = ALIGN(4);
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
index 596a9e0..b452f20 100644
--- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
@@ -61,7 +61,6 @@ SECTIONS
 	__image_copy_end = .;
 	__rel_dyn_start = .;
 	__rel_dyn_end = .;
-	__dynsym_start = .;
 
 	__got_start = .;
 	. = ALIGN(4);
diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
index 6d4b187..f359112 100644
--- a/board/dvlhost/u-boot.lds
+++ b/board/dvlhost/u-boot.lds
@@ -30,6 +30,7 @@ SECTIONS
 
 	. = ALIGN (4);
 	.text : {
+		*(.__image_copy_start)
 		arch/arm/cpu/ixp/start.o(.text*)
 		net/libnet.o(.text*)
 		board/dvlhost/libdvlhost.o(.text*)
@@ -62,17 +63,23 @@ SECTIONS
 
 	. = ALIGN (4);
 
-	__image_copy_end = .;
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
 
 	.rel.dyn : {
-		__rel_dyn_start = .;
 		*(.rel*)
-		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
 	}
 
 	_end = .;
@@ -96,6 +103,7 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	}
 
+	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }
 	/DISCARD/ : { *(.dynamic*) }
 	/DISCARD/ : { *(.plt*) }
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 29cc41b..1416f98 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -52,6 +52,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
 #else
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -137,6 +146,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 16, BOOKE_PAGESZ_256M, 1),
 #endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
index 6f4cb26..2e829ad 100644
--- a/board/freescale/bsc9131rdb/Makefile
+++ b/board/freescale/bsc9131rdb/Makefile
@@ -24,12 +24,28 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y	+= spl_minimal.o tlb.o law.o
+
+else
+
 COBJS-y        += $(BOARD).o
 COBJS-y        += ddr.o
 COBJS-y        += law.o
 COBJS-y        += tlb.o
 #COBJS-y		+= bsc9131rdb_mux.o
 
+endif
+
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
 SOBJS  := $(addprefix $(obj),$(SOBJS))
diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README
index 065faa3..4902b98 100644
--- a/board/freescale/bsc9131rdb/README
+++ b/board/freescale/bsc9131rdb/README
@@ -89,10 +89,14 @@ NAND boot
 Building U-boot
 --------------
 To build the u-boot for BSC9131RDB:
-1. NAND Flash
+1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
 	make BSC9131RDB_NAND
-2. SPI Flash
+2. NAND Flash with sysclk 100MHz(J16 on RDB open)
+	make BSC9131RDB_NAND_SYSCLK100
+3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
 	make BSC9131RDB_SPIFLASH
+4. SPI Flash with sysclk 100MHz(J16 on RDB open)
+	make BSC9131RDB_SPIFLASH_SYSCLK100
 
 Memory map
 -----------
@@ -107,6 +111,16 @@ Memory map
  0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
  0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND Buffer 8M
 
+DDR Memory map
+---------------
+ 0x0000_0000	0x36FF_FFFF	Memory passed onto Linux
+ 0x3700_0000	0x37FF_FFFF	PowerPC-DSP shared control area
+ 0x3800_0000	0x4FFF_FFFF	DSP Private area
+
+ Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
+ data communcation between PowerPC and DSP core.
+ Rest is PowerPC private area.
+
 Flashing Images
 ---------------
 To place a new u-boot image in the NAND flash and then boot
diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c
index 201c147..0432780 100644
--- a/board/freescale/bsc9131rdb/law.c
+++ b/board/freescale/bsc9131rdb/law.c
@@ -26,6 +26,10 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
+		LAW_TRGT_IF_DSP_CCSR),
+	SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
+		LAW_TRGT_IF_OCN_DSP),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
new file mode 100644
index 0000000..301115e
--- /dev/null
+++ b/board/freescale/bsc9131rdb/spl_minimal.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+static void sdram_init(void)
+{
+	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+
+	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
+#endif
+	__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+
+	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+	__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+
+	__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+
+	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+
+	/* Set, but do not enable the memory */
+	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
+
+	asm volatile("sync;isync");
+	udelay(500);
+
+	/* Let the controller go */
+	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+	set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* Initialize the DDR3 */
+	sdram_init();
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
index 5b68f4a..c05a556 100644
--- a/board/freescale/bsc9131rdb/tlb.c
+++ b/board/freescale/bsc9131rdb/tlb.c
@@ -44,15 +44,26 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 0, BOOKE_PAGESZ_4K, 1),
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
 	/* *I*G* - CCSRBAR (PA) */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT)
+	/* CCSRBAR (DSP) */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
+		      CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if  defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 8, BOOKE_PAGESZ_1G, 1),
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
index 267400b..72b1917 100644
--- a/board/freescale/bsc9132qds/Makefile
+++ b/board/freescale/bsc9132qds/Makefile
@@ -24,11 +24,28 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y	+= spl_minimal.o tlb.o law.o
+
+else
+
+
 COBJS-y	+= $(BOARD).o
 COBJS-y	+= ddr.o
 COBJS-y	+= law.o
 COBJS-y	+= tlb.o
 
+endif
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index 6e1b558..ddc9d0a 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -258,7 +258,7 @@ int misc_init_r(void)
 	u8 val;
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u32 porbmsr = in_be32(&gur->porbmsr);
-	u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
 
 	/*Configure 1588 clock-in source from RF Card*/
 	val = QIXIS_READ_I2C(brdcfg[5]);
@@ -360,7 +360,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u32 porbmsr = in_be32(&gur->porbmsr);
-	u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
 
 	if (!(hwconfig("uart2") && hwconfig("usb1"))) {
 		/* If uart2 is there in hwconfig remove usb node from
diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c
index dc23658..b4bce99 100644
--- a/board/freescale/bsc9132qds/law.c
+++ b/board/freescale/bsc9132qds/law.c
@@ -25,11 +25,13 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_SYS_NO_FLASH
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
-#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_FPGA_BASE_PHYS
 	SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
new file mode 100644
index 0000000..62dee52
--- /dev/null
+++ b/board/freescale/bsc9132qds/spl_minimal.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_init(void)
+{
+	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+#if CONFIG_DDR_CLK_FREQ == 100000000
+	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+
+	__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
+	__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
+	__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
+	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
+	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
+
+	__raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5);
+	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+#elif CONFIG_DDR_CLK_FREQ == 133000000
+	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
+	__raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+
+	__raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2);
+	__raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode);
+	__raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2);
+	__raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval);
+	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl);
+	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl);
+
+	__raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4);
+	__raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
+	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+#else
+	puts("Not a valid DDR Freq Found! Please Reset\n");
+#endif
+	asm volatile("sync;isync");
+	udelay(500);
+
+	/* Let the controller go */
+	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+	set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* initialize selected port with appropriate baud rate */
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* Initialize the DDR3 */
+	sdram_init();
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
index 0e4545f..0ec9a85 100644
--- a/board/freescale/bsc9132qds/tlb.c
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -44,14 +44,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 0, BOOKE_PAGESZ_4K, 1),
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
 	/* *I*G* - CCSRBAR (PA) */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
+#ifndef CONFIG_SPL_BUILD
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 3, BOOKE_PAGESZ_64M, 1),
@@ -61,12 +67,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 4, BOOKE_PAGESZ_64M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
 #ifdef CONFIG_PCI
 	/* *I*G* - PCI */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
@@ -78,15 +78,26 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 7, BOOKE_PAGESZ_64K, 1),
 #endif
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
 
+#ifdef CONFIG_SYS_FPGA_BASE
 		/* *I*G - Board FPGA  */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 9, BOOKE_PAGESZ_256K, 1),
+#endif
 
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 5, BOOKE_PAGESZ_1M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 72bb56c..37236d0 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -29,6 +29,15 @@ endif
 
 LIB	= $(obj)libfreescale.o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifndef MINIMAL
 COBJS-$(CONFIG_FSL_CADMUS)	+= cadmus.o
 COBJS-$(CONFIG_FSL_VIA)		+= cds_via.o
 COBJS-$(CONFIG_FMAN_ENET)	+= fman.o
@@ -68,6 +77,7 @@ SUBLIB-$(CONFIG_P3041DS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P4080DS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P5020DS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P5040DS)	+= p_corenet/libp_corenet.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index 8d07061..fbb709d 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -480,6 +480,7 @@ static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
 	    ||	unknown_param) {
 #ifdef CONFIG_SYS_LONGHELP
 		puts(cmdtp->help);
+		putc('\n');
 #endif
 		return 1;
 	}
@@ -512,6 +513,7 @@ static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
 		      && set_px_mpxpll(mpxpll))) {
 #ifdef CONFIG_SYS_LONGHELP
 			puts(cmdtp->help);
+			putc('\n');
 #endif
 			return 1;
 		}
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 4969960..963d29f 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -34,6 +34,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text	   :
 	{
+		*(.__image_copy_start)
 	  /* WARNING - the following is hand-optimized to fit within	*/
 	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
 
@@ -65,17 +66,23 @@ SECTIONS
 
 	. = ALIGN(4);
 
-	__image_copy_end = .;
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
 
 	.rel.dyn : {
-		__rel_dyn_start = .;
 		*(.rel*)
-		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
 	}
 
 	_end = .;
@@ -100,6 +107,7 @@ SECTIONS
 	}
 
 	/DISCARD/ : { *(.bss*) }
+	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }
 	/DISCARD/ : { *(.dynsym*) }
 	/DISCARD/ : { *(.dynamic*) }
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index 4c705b6..e6563be 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y	+= spl_minimal.o tlb.o law.o
+
+else
+
 COBJS-y	+= $(BOARD).o
 COBJS-y	+= ddr.o
 COBJS-y	+= law.o
 COBJS-y	+= tlb.o
 
+endif
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/board/freescale/p1010rdb/spl_minimal.c
similarity index 95%
rename from nand_spl/board/freescale/p1010rdb/nand_boot.c
rename to board/freescale/p1010rdb/spl_minimal.c
index 3c7bc2b..c909e0e 100644
--- a/nand_spl/board/freescale/p1010rdb/nand_boot.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -31,11 +31,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned long ddr_freq_mhz;
 
 void sdram_init(void)
 {
 	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	u32 ddr_ratio;
+	unsigned long ddr_freq_mhz;
+
+	ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+	ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+	ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
+
 	/* mask off E bit */
 	u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
 
@@ -81,6 +88,7 @@ void sdram_init(void)
 		__raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
 	}
 
+	asm volatile("sync;isync");
 	udelay(500);
 
 	/* Let the controller go */
@@ -91,7 +99,7 @@ void sdram_init(void)
 
 void board_init_f(ulong bootflag)
 {
-	u32 plat_ratio, ddr_ratio;
+	u32 plat_ratio;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
 	/* initialize selected port with appropriate baud rate */
@@ -99,10 +107,6 @@ void board_init_f(ulong bootflag)
 	plat_ratio >>= 1;
 	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
 
-	ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
-	ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-	ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
-
 	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
 			gd->bus_clk / 16 / CONFIG_BAUDRATE);
 
@@ -115,8 +119,8 @@ void board_init_f(ulong bootflag)
 	/* NOTE - code has to be copied out of NAND buffer before
 	 * other blocks can be read.
 	 */
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
-			CONFIG_SYS_NAND_U_BOOT_RELOC);
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
 }
 
 void board_init_r(gd_t *gd, ulong dest_addr)
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index 4256bf4..078717a 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -44,15 +44,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 0, BOOKE_PAGESZ_4K, 1),
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SPL_NAND_MINIMAL
+	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_4K, 1),
+#endif
 
 	/* *I*G* - CCSRBAR */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 1, BOOKE_PAGESZ_1M, 1),
 
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
 #ifndef CONFIG_SDCARD
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
@@ -88,7 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 7, BOOKE_PAGESZ_1M, 1),
 #endif
 
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 8, BOOKE_PAGESZ_1G, 1)
diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile
new file mode 100644
index 0000000..45c4f8b
--- /dev/null
+++ b/board/freescale/p1023rdb/Makefile
@@ -0,0 +1,33 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
new file mode 100644
index 0000000..7ed275a
--- /dev/null
+++ b/board/freescale/p1023rdb/ddr.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* CONFIG_SYS_DDR_RAW_TIMING */
+/*
+ * Hynix H5TQ1G83TFR-H9C
+ */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 536870912u,
+	.capacity = 536870912u,
+	.primary_sdram_width = 32,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tCKmin_X_ps = 1875,
+	.caslat_X = 0x1e << 4,	/* 5,6,7,8 */
+	.tAA_ps = 13125,
+	.tWR_ps = 18000,
+	.tRCD_ps = 13125,
+	.tRRD_ps = 7500,
+	.tRP_ps = 13125,
+	.tRAS_ps = 37500,
+	.tRC_ps = 50625,
+	.tRFC_ps = 160000,
+	.tWTR_ps = 7500,
+	.tRTP_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tFAW_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	int i;
+	popts->clk_adjust = 6;
+	popts->cpo_override = 0x1f;
+	popts->write_data_delay = 2;
+	popts->half_strength_driver_enable = 1;
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start = 0x8;
+	popts->trwt_override = 1;
+	popts->trwt = 0;
+
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+	}
+}
+
diff --git a/board/freescale/p1023rdb/law.c b/board/freescale/p1023rdb/law.c
new file mode 100644
index 0000000..331662c
--- /dev/null
+++ b/board/freescale/p1023rdb/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
+		LAW_TRGT_IF_DPAA_SWP_SRAM),
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
new file mode 100644
index 0000000..918398b
--- /dev/null
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors:  Roy Zang <tie-fei.zang@freescale.com>
+ *           Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_portals.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	/* Set ABSWP to implement conversion of addresses in the LBC */
+	setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: P1023 RDB\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	setup_portals();
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	return gd->bus_clk;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+	return gd->mem_clk;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	struct fsl_pq_mdio_info dtsec_mdio_info;
+
+	/*
+	 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
+	 * is not correct.
+	 */
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
+
+	dtsec_mdio_info.regs =
+		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+
+	fm_info_set_mdio(FM1_DTSEC1,
+			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+	fm_info_set_mdio(FM1_DTSEC2,
+			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+#ifdef CONFIG_FMAN_ENET
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
+	fdt_fixup_fman_ethernet(blob);
+}
+#endif
diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c
new file mode 100644
index 0000000..3417c0f
--- /dev/null
+++ b/board/freescale/p1023rdb/tlb.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_4M, 1),
+
+	/* W**G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* Bman/Qman */
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, 0,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_M,
+		      0, 9, BOOKE_PAGESZ_1M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_1M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 11, BOOKE_PAGESZ_16K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
+		      CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 12, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		      CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 13, BOOKE_PAGESZ_256M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 92c01cf..a138d5a 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -55,6 +55,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
 #else
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -130,6 +139,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 17, BOOKE_PAGESZ_4K, 1),
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
 
 };
 
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 826cead..ea3bea5 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -36,37 +36,13 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define RMII_MODE_ENABLE	0x4D
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
-/* UART Defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET		(0x1 << 1)
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
-	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-	/*
-	 * Unlock the RTC's registers.  For more details please see the
-	 * RTC_SS section of the TRM.  In order to unlock we need to
-	 * write these specific values (keys) in this order.
-	 */
-	writel(0x83e70b13, &rtc->kick0r);
-	writel(0x95a4f1e0, &rtc->kick1r);
-
-	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
-	writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
 	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
@@ -131,23 +107,9 @@ void s_init(void)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
 
-	/* UART softreset */
-	u32 regval;
-
 	enable_uart0_pin_mux();
 
-	regval = readl(&uart_base->uartsyscfg);
-	regval |= UART_RESET;
-	writel(regval, &uart_base->uartsyscfg);
-	while ((readl(&uart_base->uartsyssts) &
-		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-		;
-
-	/* Disable smart idle */
-	regval = readl(&uart_base->uartsyscfg);
-	regval |= UART_SMART_IDLE_EN;
-	writel(regval, &uart_base->uartsyscfg);
-
+	uart_soft_reset();
 	gd = &gdata;
 
 	preloader_console_init();
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 93c611d..0cca8d7 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -39,9 +39,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define MII_MODE_ENABLE		0x0
@@ -50,31 +47,11 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
-/* UART defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET		(0x1 << 1)
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
 
 /* DDR RAM defines */
 #define DDR_CLK_MHZ		303 /* DDR_DPLL_MULT value */
 
-static void rtc32k_enable(void)
-{
-	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-	/*
-	 * Unlock the RTC's registers.  For more details please see the
-	 * RTC_SS section of the TRM.  In order to unlock we need to
-	 * write these specific values (keys) in this order.
-	 */
-	writel(0x83e70b13, &rtc->kick0r);
-	writel(0x95a4f1e0, &rtc->kick1r);
-
-	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
-	writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
 	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
@@ -141,22 +118,8 @@ void s_init(void)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
 
-	/* UART softreset */
-	u32 regval;
-
 	enable_uart0_pin_mux();
-
-	regval = readl(&uart_base->uartsyscfg);
-	regval |= UART_RESET;
-	writel(regval, &uart_base->uartsyscfg);
-	while ((readl(&uart_base->uartsyssts) &	UART_CLK_RUNNING_MASK)
-		!= UART_CLK_RUNNING_MASK)
-		;
-
-	/* Disable smart idle */
-	regval = readl(&uart_base->uartsyscfg);
-	regval |= UART_SMART_IDLE_EN;
-	writel(regval, &uart_base->uartsyscfg);
+	uart_soft_reset();
 
 	gd = &gdata;
 
diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts
index 8da973b..93375a6 100644
--- a/board/samsung/dts/exynos5250-smdk5250.dts
+++ b/board/samsung/dts/exynos5250-smdk5250.dts
@@ -30,6 +30,10 @@
 		spi2 = "/spi@12d40000";
 		spi3 = "/spi@131a0000";
 		spi4 = "/spi@131b0000";
+		mmc0 = "/mmc@12200000";
+		mmc1 = "/mmc@12210000";
+		mmc2 = "/mmc@12220000";
+		mmc3 = "/mmc@12230000";
 	};
 
 	sromc@12250000 {
@@ -119,4 +123,24 @@
 		samsung,ycbcr-coeff = <0>;
 		samsung,color-depth = <1>;
 	};
+
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		samsung,removable = <0>;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		samsung,removable = <1>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
 };
diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
index 9daa0da..be9d418 100644
--- a/board/samsung/origen/lowlevel_init.S
+++ b/board/samsung/origen/lowlevel_init.S
@@ -87,12 +87,14 @@ lowlevel_init:
 1:
 	/* for UART */
 	bl uart_asm_init
+	bl arch_cpu_init
 	bl tzpc_init
 	pop	{pc}
 
 wakeup_reset:
 	bl system_clock_init
 	bl mem_ctrl_asm_init
+	bl arch_cpu_init
 	bl tzpc_init
 
 exit_wakeup:
@@ -353,45 +355,3 @@ uart_asm_init:
 	nop
 	nop
 
-/* Setting TZPC[TrustZone Protection Controller] */
-tzpc_init:
-	ldr	r0, =TZPC0_BASE
-	mov	r1, #R0SIZE
-	str	r1, [r0]
-	mov	r1, #DECPROTXSET
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	ldr	r0, =TZPC1_BASE
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	ldr	r0, =TZPC2_BASE
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	ldr	r0, =TZPC3_BASE
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	ldr	r0, =TZPC4_BASE
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	ldr	r0, =TZPC5_BASE
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	mov	pc, lr
diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
index 930b948..926a4cc 100644
--- a/board/samsung/origen/origen_setup.h
+++ b/board/samsung/origen/origen_setup.h
@@ -121,19 +121,6 @@
 #define UBRDIV_OFFSET		0x28
 #define UFRACVAL_OFFSET		0x2C
 
-/* TZPC : Register Offsets */
-#define TZPC0_BASE		0x10110000
-#define TZPC1_BASE		0x10120000
-#define TZPC2_BASE		0x10130000
-#define TZPC3_BASE		0x10140000
-#define TZPC4_BASE		0x10150000
-#define TZPC5_BASE		0x10160000
-
-#define TZPC_DECPROT0SET_OFFSET	0x804
-#define TZPC_DECPROT1SET_OFFSET	0x810
-#define TZPC_DECPROT2SET_OFFSET	0x81C
-#define TZPC_DECPROT3SET_OFFSET	0x828
-
 /* CLK_SRC_CPU */
 #define MUX_HPM_SEL_MOUTAPLL		0x0
 #define MUX_HPM_SEL_SCLKMPLL		0x1
@@ -617,16 +604,4 @@
  * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
  */
 #define UFRACVAL_VAL		0x4
-
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE			0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET		0xFF
 #endif
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 47c6a5a..f2c32ee 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -28,12 +28,15 @@ SOBJS	:= lowlevel_init.o
 
 COBJS	:= clock_init.o
 COBJS	+= dmc_common.o dmc_init_ddr3.o
-COBJS	+= tzpc_init.o
 COBJS	+= smdk5250_spl.o
 
 ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_OF_CONTROL
+COBJS	+= exynos5-dt.o
+else
 COBJS	+= smdk5250.o
 endif
+endif
 
 ifdef CONFIG_SPL_BUILD
 COBJS	+= spl_boot.o
diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c
index 5b9e82f..b288e66 100644
--- a/board/samsung/smdk5250/clock_init.c
+++ b/board/samsung/smdk5250/clock_init.c
@@ -28,10 +28,14 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/spl.h>
+#include <asm/arch/dwmmc.h>
 
 #include "clock_init.h"
 #include "setup.h"
 
+#define FSYS1_MMC0_DIV_MASK	0xff0f
+#define FSYS1_MMC0_DIV_VAL	0x0701
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct arm_clk_ratios arm_clk_ratios[] = {
@@ -664,3 +668,17 @@ void clock_init_dp_clock(void)
 	/* We run DP at 267 Mhz */
 	setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
 }
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
+ */
+void emmc_boot_clk_div_set(void)
+{
+	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+	unsigned int div_mmc;
+
+	div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
+	div_mmc |= FSYS1_MMC0_DIV_VAL;
+	writel(div_mmc, (unsigned int) &clk->div_fsys1);
+}
diff --git a/board/samsung/smdk5250/clock_init.h b/board/samsung/smdk5250/clock_init.h
index f751bcb..20a1d47 100644
--- a/board/samsung/smdk5250/clock_init.h
+++ b/board/samsung/smdk5250/clock_init.h
@@ -146,4 +146,9 @@ struct mem_timings *clock_get_mem_timings(void);
  * Initialize clock for the device
  */
 void system_clock_init(void);
+
+/*
+ * Set clock divisor value for booting from EMMC.
+ */
+void emmc_boot_clk_div_set(void);
 #endif
diff --git a/board/samsung/smdk5250/exynos5-dt.c b/board/samsung/smdk5250/exynos5-dt.c
new file mode 100644
index 0000000..8131505
--- /dev/null
+++ b/board/samsung/smdk5250/exynos5-dt.c
@@ -0,0 +1,423 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <spi.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
+#include <asm/arch/sromc.h>
+#include <power/pmic.h>
+#include <power/max77686_pmic.h>
+#include <tmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined CONFIG_EXYNOS_TMU
+/*
+ * Boot Time Thermal Analysis for SoC temperature threshold breach
+ */
+static void boot_temp_check(void)
+{
+	int temp;
+
+	switch (tmu_monitor(&temp)) {
+	/* Status TRIPPED ans WARNING means corresponding threshold breach */
+	case TMU_STATUS_TRIPPED:
+		puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
+		set_ps_hold_ctrl();
+		hang();
+		break;
+	case TMU_STATUS_WARNING:
+		puts("EXYNOS_TMU: WARNING! Temperature very high\n");
+		break;
+	/*
+	 * TMU_STATUS_INIT means something is wrong with temperature sensing
+	 * and TMU status was changed back from NORMAL to INIT.
+	 */
+	case TMU_STATUS_INIT:
+	default:
+		debug("EXYNOS_TMU: Unknown TMU state\n");
+	}
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_vbus_init(void)
+{
+	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+						samsung_get_base_gpio_part1();
+
+	/* Enable VBUS power switch */
+	s5p_gpio_direction_output(&gpio1->x2, 6, 1);
+
+	/* VBUS turn ON time */
+	mdelay(3);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SOUND_MAX98095
+static void  board_enable_audio_codec(void)
+{
+	struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+						samsung_get_base_gpio_part1();
+
+	/* Enable MAX98095 Codec */
+	s5p_gpio_direction_output(&gpio1->x1, 7, 1);
+	s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
+}
+#endif
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+
+#if defined CONFIG_EXYNOS_TMU
+	if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
+		debug("%s: Failed to init TMU\n", __func__);
+		return -1;
+	}
+	boot_temp_check();
+#endif
+
+#ifdef CONFIG_EXYNOS_SPI
+	spi_init();
+#endif
+#ifdef CONFIG_USB_EHCI_EXYNOS
+	board_usb_vbus_init();
+#endif
+#ifdef CONFIG_SOUND_MAX98095
+	board_enable_audio_codec();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	int i;
+	u32 addr;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+	}
+	return 0;
+}
+
+#if defined(CONFIG_POWER)
+static int pmic_reg_update(struct pmic *p, int reg, uint regval)
+{
+	u32 val;
+	int ret = 0;
+
+	ret = pmic_reg_read(p, reg, &val);
+	if (ret) {
+		debug("%s: PMIC %d register read failed\n", __func__, reg);
+		return -1;
+	}
+	val |= regval;
+	ret = pmic_reg_write(p, reg, val);
+	if (ret) {
+		debug("%s: PMIC %d register write failed\n", __func__, reg);
+		return -1;
+	}
+	return 0;
+}
+
+int power_init_board(void)
+{
+	struct pmic *p;
+
+	set_ps_hold_ctrl();
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	if (pmic_init(I2C_PMIC))
+		return -1;
+
+	p = pmic_get("MAX77686_PMIC");
+	if (!p)
+		return -ENODEV;
+
+	if (pmic_probe(p))
+		return -1;
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
+		return -1;
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
+			    MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
+		return -1;
+
+	/* VDD_MIF */
+	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
+			   MAX77686_BUCK1OUT_1V)) {
+		debug("%s: PMIC %d register write failed\n", __func__,
+		      MAX77686_REG_PMIC_BUCK1OUT);
+		return -1;
+	}
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
+			    MAX77686_BUCK1CTRL_EN))
+		return -1;
+
+	/* VDD_ARM */
+	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
+			   MAX77686_BUCK2DVS1_1_3V)) {
+		debug("%s: PMIC %d register write failed\n", __func__,
+		      MAX77686_REG_PMIC_BUCK2DVS1);
+		return -1;
+	}
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
+			    MAX77686_BUCK2CTRL_ON))
+		return -1;
+
+	/* VDD_INT */
+	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
+			   MAX77686_BUCK3DVS1_1_0125V)) {
+		debug("%s: PMIC %d register write failed\n", __func__,
+		      MAX77686_REG_PMIC_BUCK3DVS1);
+		return -1;
+	}
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
+			    MAX77686_BUCK3CTRL_ON))
+		return -1;
+
+	/* VDD_G3D */
+	if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
+			   MAX77686_BUCK4DVS1_1_2V)) {
+		debug("%s: PMIC %d register write failed\n", __func__,
+		      MAX77686_REG_PMIC_BUCK4DVS1);
+		return -1;
+	}
+
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
+			    MAX77686_BUCK3CTRL_ON))
+		return -1;
+
+	/* VDD_LDO2 */
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
+			    MAX77686_LD02CTRL1_1_5V | EN_LDO))
+		return -1;
+
+	/* VDD_LDO3 */
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
+			    MAX77686_LD03CTRL1_1_8V | EN_LDO))
+		return -1;
+
+	/* VDD_LDO5 */
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
+			    MAX77686_LD05CTRL1_1_8V | EN_LDO))
+		return -1;
+
+	/* VDD_LDO10 */
+	if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
+			    MAX77686_LD10CTRL1_1_8V | EN_LDO))
+		return -1;
+
+	return 0;
+}
+#endif
+
+void dram_init_banksize(void)
+{
+	int i;
+	u32 addr, size;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+
+		gd->bd->bi_dram[i].start = addr;
+		gd->bd->bi_dram[i].size = size;
+	}
+}
+
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+	int err;
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+	if (node < 0) {
+		debug("Could not find SROMC node\n");
+		return node;
+	}
+
+	config->bank = fdtdec_get_int(blob, node, "bank", 0);
+	config->width = fdtdec_get_int(blob, node, "width", 2);
+
+	err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+			FDT_SROM_TIMING_COUNT);
+	if (err < 0) {
+		debug("Could not decode SROMC configuration Error: %s\n",
+		      fdt_strerror(err));
+		return -FDT_ERR_NOTFOUND;
+	}
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SMC911X
+	u32 smc_bw_conf, smc_bc_conf;
+	struct fdt_sromc config;
+	fdt_addr_t base_addr;
+	int node;
+
+	node = decode_sromc(gd->fdt_blob, &config);
+	if (node < 0) {
+		debug("%s: Could not find sromc configuration\n", __func__);
+		return 0;
+	}
+	node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+	if (node < 0) {
+		debug("%s: Could not find lan9215 configuration\n", __func__);
+		return 0;
+	}
+
+	/* We now have a node, so any problems from now on are errors */
+	base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+	if (base_addr == FDT_ADDR_T_NONE) {
+		debug("%s: Could not find lan9215 address\n", __func__);
+		return -1;
+	}
+
+	/* Ethernet needs data bus width of 16 bits */
+	if (config.width != 2) {
+		debug("%s: Unsupported bus width %d\n", __func__,
+		      config.width);
+		return -1;
+	}
+	smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+			| SROMC_BYTE_ENABLE(config.bank);
+
+	smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |
+			SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
+			SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
+			SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
+			SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |
+			SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
+			SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+	/* Select and configure the SROMC bank */
+	exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+	s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+	return smc911x_initialize(0, base_addr);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	const char *board_name;
+
+	board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
+	if (board_name == NULL)
+		printf("\nUnknown Board\n");
+	else
+		printf("\nBoard: %s\n", board_name);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+	/* dwmmc initializattion for available channels */
+	ret = exynos_dwmmc_init(gd->fdt_blob);
+	if (ret)
+		debug("dwmmc init failed\n");
+
+	return ret;
+}
+#endif
+
+static int board_uart_init(void)
+{
+	int err, uart_id, ret = 0;
+
+	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+		err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+		if (err) {
+			debug("UART%d not configured\n",
+			      (uart_id - PERIPH_ID_UART0));
+			ret |= err;
+		}
+	}
+	return ret;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	int err;
+	err = board_uart_init();
+	if (err) {
+		debug("UART init failed\n");
+		return err;
+	}
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+	board_i2c_init(gd->fdt_blob);
+#endif
+	return err;
+}
+#endif
+
+#ifdef CONFIG_LCD
+void exynos_cfg_lcd_gpio(void)
+{
+	struct exynos5_gpio_part1 *gpio1 =
+		(struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
+
+	/* For Backlight */
+	s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+	s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+	/* LCD power on */
+	s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+	s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+	/* Set Hotplug detect for DP */
+	s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+void exynos_set_dp_phy(unsigned int onoff)
+{
+	set_dp_phy_ctrl(onoff);
+}
+#endif
diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S
index bc6cb6f..edc565e 100644
--- a/board/samsung/smdk5250/lowlevel_init.S
+++ b/board/samsung/smdk5250/lowlevel_init.S
@@ -75,12 +75,14 @@ lowlevel_init:
 	bl	mem_ctrl_init
 
 1:
+	bl	arch_cpu_init
 	bl	tzpc_init
 	ldmia	r13!, {ip,pc}
 
 wakeup_reset:
 	bl	system_clock_init
 	bl	mem_ctrl_init
+	bl	arch_cpu_init
 	bl	tzpc_init
 
 exit_wakeup:
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
index 34d8bc31..eb91d13 100644
--- a/board/samsung/smdk5250/setup.h
+++ b/board/samsung/smdk5250/setup.h
@@ -28,18 +28,6 @@
 #include <config.h>
 #include <asm/arch/dmc.h>
 
-/* TZPC : Register Offsets */
-#define TZPC0_BASE		0x10100000
-#define TZPC1_BASE		0x10110000
-#define TZPC2_BASE		0x10120000
-#define TZPC3_BASE		0x10130000
-#define TZPC4_BASE		0x10140000
-#define TZPC5_BASE		0x10150000
-#define TZPC6_BASE		0x10160000
-#define TZPC7_BASE		0x10170000
-#define TZPC8_BASE		0x10180000
-#define TZPC9_BASE		0x10190000
-
 /* APLL_CON1	*/
 #define APLL_CON1_VAL	(0x00203800)
 
@@ -458,18 +446,6 @@
 /* CLK_GATE_IP_DISP1 */
 #define CLK_GATE_DP1_ALLOW	(1 << 4)
 
-/*
- * TZPC Register Value :
- * R0SIZE: 0x0 : Size of secured ram
- */
-#define R0SIZE			0x0
-
-/*
- * TZPC Decode Protection Register Value :
- * DECPROTXSET: 0xFF : Set Decode region to non-secure
- */
-#define DECPROTXSET		0xFF
-
 #define DDR3PHY_CTRL_PHY_RESET	(1 << 0)
 #define DDR3PHY_CTRL_PHY_RESET_OFF	(0 << 0)
 
@@ -590,5 +566,4 @@ void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
 void sdelay(unsigned long);
 void mem_ctrl_init(void);
 void system_clock_init(void);
-void tzpc_init(void);
 #endif
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
index 8b09e1d..276fd41 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -29,6 +29,7 @@
 #include <netdev.h>
 #include <spi.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/dwmmc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
@@ -37,39 +38,9 @@
 #include <asm/arch/dp_info.h>
 #include <power/pmic.h>
 #include <power/max77686_pmic.h>
-#include <tmu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined CONFIG_EXYNOS_TMU
-/*
- * Boot Time Thermal Analysis for SoC temperature threshold breach
- */
-static void boot_temp_check(void)
-{
-	int temp;
-
-	switch (tmu_monitor(&temp)) {
-	/* Status TRIPPED ans WARNING means corresponding threshold breach */
-	case TMU_STATUS_TRIPPED:
-		puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
-		set_ps_hold_ctrl();
-		hang();
-		break;
-	case TMU_STATUS_WARNING:
-		puts("EXYNOS_TMU: WARNING! Temperature very high\n");
-		break;
-	/*
-	 * TMU_STATUS_INIT means something is wrong with temperature sensing
-	 * and TMU status was changed back from NORMAL to INIT.
-	 */
-	case TMU_STATUS_INIT:
-	default:
-		debug("EXYNOS_TMU: Unknown TMU state\n");
-	}
-}
-#endif
-
 #ifdef CONFIG_USB_EHCI_EXYNOS
 int board_usb_vbus_init(void)
 {
@@ -102,14 +73,6 @@ int board_init(void)
 {
 	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 
-#if defined CONFIG_EXYNOS_TMU
-	if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
-		debug("%s: Failed to init TMU\n", __func__);
-		return -1;
-	}
-	boot_temp_check();
-#endif
-
 #ifdef CONFIG_EXYNOS_SPI
 	spi_init();
 #endif
@@ -124,14 +87,13 @@ int board_init(void)
 
 int dram_init(void)
 {
-	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
+	int i;
+	u32 addr;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+	}
 	return 0;
 }
 
@@ -254,57 +216,15 @@ int power_init_board(void)
 
 void dram_init_banksize(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
-							PHYS_SDRAM_1_SIZE);
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
-							PHYS_SDRAM_2_SIZE);
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
-							PHYS_SDRAM_3_SIZE);
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
-							PHYS_SDRAM_4_SIZE);
-	gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
-	gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
-							PHYS_SDRAM_5_SIZE);
-	gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
-	gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
-							PHYS_SDRAM_6_SIZE);
-	gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
-	gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
-							PHYS_SDRAM_7_SIZE);
-	gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
-	gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
-							PHYS_SDRAM_8_SIZE);
-}
-
-#ifdef CONFIG_OF_CONTROL
-static int decode_sromc(const void *blob, struct fdt_sromc *config)
-{
-	int err;
-	int node;
-
-	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
-	if (node < 0) {
-		debug("Could not find SROMC node\n");
-		return node;
-	}
-
-	config->bank = fdtdec_get_int(blob, node, "bank", 0);
-	config->width = fdtdec_get_int(blob, node, "width", 2);
-
-	err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
-			FDT_SROM_TIMING_COUNT);
-	if (err < 0) {
-		debug("Could not decode SROMC configuration\n");
-		return -FDT_ERR_NOTFOUND;
+	int i;
+	u32 addr, size;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
+		size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
+		gd->bd->bi_dram[i].start = addr;
+		gd->bd->bi_dram[i].size = size;
 	}
-
-	return 0;
 }
-#endif
 
 int board_eth_init(bd_t *bis)
 {
@@ -313,27 +233,6 @@ int board_eth_init(bd_t *bis)
 	struct fdt_sromc config;
 	fdt_addr_t base_addr;
 
-#ifdef CONFIG_OF_CONTROL
-	int node;
-
-	node = decode_sromc(gd->fdt_blob, &config);
-	if (node < 0) {
-		debug("%s: Could not find sromc configuration\n", __func__);
-		return 0;
-	}
-	node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
-	if (node < 0) {
-		debug("%s: Could not find lan9215 configuration\n", __func__);
-		return 0;
-	}
-
-	/* We now have a node, so any problems from now on are errors */
-	base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
-	if (base_addr == FDT_ADDR_T_NONE) {
-		debug("%s: Could not find lan9215 address\n", __func__);
-		return -1;
-	}
-#else
 	/* Non-FDT configuration - bank number and timing parameters*/
 	config.bank = CONFIG_ENV_SROM_BANK;
 	config.width = 2;
@@ -346,7 +245,6 @@ int board_eth_init(bd_t *bis)
 	config.timing[FDT_SROM_TACP] = 0x09;
 	config.timing[FDT_SROM_PMC] = 0x01;
 	base_addr = CONFIG_SMC911X_BASE;
-#endif
 
 	/* Ethernet needs data bus width of 16 bits */
 	if (config.width != 2) {
@@ -376,17 +274,7 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_DISPLAY_BOARDINFO
 int checkboard(void)
 {
-#ifdef CONFIG_OF_CONTROL
-	const char *board_name;
-
-	board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
-	if (board_name == NULL)
-		printf("\nUnknown Board\n");
-	else
-		printf("\nBoard: %s\n", board_name);
-#else
 	printf("\nBoard: SMDK5250\n");
-#endif
 	return 0;
 }
 #endif
@@ -394,48 +282,54 @@ int checkboard(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-	int err;
+	int err, ret = 0, index, bus_width;
+	u32 base;
 
 	err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
-	if (err) {
+	if (err)
 		debug("SDMMC0 not configured\n");
-		return err;
-	}
-
-	err = s5p_mmc_init(0, 8);
-	return err;
+	ret |= err;
+
+	/*EMMC: dwmmc Channel-0 with 8 bit bus width */
+	index = 0;
+	base =  samsung_get_base_mmc() + (0x10000 * index);
+	bus_width = 8;
+	err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
+	if (err)
+		debug("dwmmc Channel-0 init failed\n");
+	ret |= err;
+
+	err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+	if (err)
+		debug("SDMMC2 not configured\n");
+	ret |= err;
+
+	/*SD: dwmmc Channel-2 with 4 bit bus width */
+	index = 2;
+	base = samsung_get_base_mmc() + (0x10000 * index);
+	bus_width = 4;
+	err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
+	if (err)
+		debug("dwmmc Channel-2 init failed\n");
+	ret |= err;
+
+	return ret;
 }
 #endif
 
 static int board_uart_init(void)
 {
-	int err;
-
-	err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART0 not configured\n");
-		return err;
+	int err, uart_id, ret = 0;
+
+	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
+		err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
+		if (err) {
+			debug("UART%d not configured\n",
+			      (uart_id - PERIPH_ID_UART0));
+			ret |= err;
+		}
 	}
-
-	err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART1 not configured\n");
-		return err;
-	}
-
-	err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART2 not configured\n");
-		return err;
-	}
-
-	err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART3 not configured\n");
-		return err;
-	}
-
-	return 0;
+	return ret;
 }
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
@@ -448,7 +342,7 @@ int board_early_init_f(void)
 		return err;
 	}
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
-	board_i2c_init(gd->fdt_blob);
+	board_i2c_init(NULL);
 #endif
 	return err;
 }
@@ -477,7 +371,6 @@ void exynos_set_dp_phy(unsigned int onoff)
 	set_dp_phy_ctrl(onoff);
 }
 
-#ifndef CONFIG_OF_CONTROL
 vidinfo_t panel_info = {
 	.vl_freq	= 60,
 	.vl_col		= 2560,
@@ -543,13 +436,9 @@ static struct exynos_dp_platform_data dp_platform_data = {
 	.edp_dev_info	= &edp_info,
 };
 
-#endif
 void init_panel_info(vidinfo_t *vid)
 {
-#ifndef CONFIG_OF_CONTROL
-	vid->rgb_mode   = MODE_RGB_P,
-
+	vid->rgb_mode   = MODE_RGB_P;
 	exynos_set_dp_platform_data(&dp_platform_data);
-#endif
 }
 #endif
diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c
index c0bcf46..98f2286 100644
--- a/board/samsung/smdk5250/spl_boot.c
+++ b/board/samsung/smdk5250/spl_boot.c
@@ -23,16 +23,44 @@
 #include<common.h>
 #include<config.h>
 
+#include <asm/arch-exynos/dmc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+
+#include "clock_init.h"
+
+/* Index into irom ptr table */
+enum index {
+	MMC_INDEX,
+	EMMC44_INDEX,
+	EMMC44_END_INDEX,
+	SPI_INDEX,
+	USB_INDEX,
+};
+
+/* IROM Function Pointers Table */
+u32 irom_ptr_table[] = {
+	[MMC_INDEX] = 0x02020030,	/* iROM Function Pointer-SDMMC boot */
+	[EMMC44_INDEX] = 0x02020044,	/* iROM Function Pointer-EMMC4.4 boot*/
+	[EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
+						-EMMC4.4 end boot operation */
+	[SPI_INDEX] = 0x02020058,	/* iROM Function Pointer-SPI boot */
+	[USB_INDEX] = 0x02020070,	/* iROM Function Pointer-USB boot*/
+	};
+
 enum boot_mode {
 	BOOT_MODE_MMC = 4,
 	BOOT_MODE_SERIAL = 20,
+	BOOT_MODE_EMMC = 8,     /* EMMC4.4 */
 	/* Boot based on Operating Mode pin settings */
 	BOOT_MODE_OM = 32,
 	BOOT_MODE_USB,	/* Boot using USB download */
 };
 
-	typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst);
-	typedef u32 (*usb_copy_func_t)(void);
+void *get_irom_func(int index)
+{
+	return (void *)*(u32 *)irom_ptr_table[index];
+}
 
 /*
  * Set/clear program flow prediction and return the previous state.
@@ -55,13 +83,15 @@ static int config_branch_prediction(int set_cr_z)
 */
 void copy_uboot_to_ram(void)
 {
-	spi_copy_func_t spi_copy;
-	usb_copy_func_t usb_copy;
-
 	int is_cr_z_set;
 	unsigned int sec_boot_check;
 	enum boot_mode bootmode = BOOT_MODE_OM;
-	u32 (*copy_bl2)(u32, u32, u32);
+
+	u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst);
+	u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst);
+	u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
+	void (*end_bootop_from_emmc)(void);
+	u32 (*usb_copy)(void);
 
 	/* Read iRAM location to check for secondary USB boot mode */
 	sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
@@ -73,14 +103,24 @@ void copy_uboot_to_ram(void)
 
 	switch (bootmode) {
 	case BOOT_MODE_SERIAL:
-		spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR;
+		spi_copy = get_irom_func(SPI_INDEX);
 		spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
-						CONFIG_SYS_TEXT_BASE);
+			 CONFIG_SYS_TEXT_BASE);
 		break;
 	case BOOT_MODE_MMC:
-		copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+		copy_bl2 = get_irom_func(MMC_INDEX);
 		copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
-						CONFIG_SYS_TEXT_BASE);
+			 CONFIG_SYS_TEXT_BASE);
+		break;
+	case BOOT_MODE_EMMC:
+		/* Set the FSYS1 clock divisor value for EMMC boot */
+		emmc_boot_clk_div_set();
+
+		copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
+		end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
+
+		copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
+		end_bootop_from_emmc();
 		break;
 	case BOOT_MODE_USB:
 		/*
@@ -88,8 +128,7 @@ void copy_uboot_to_ram(void)
 		 * before copy from USB device to RAM
 		 */
 		is_cr_z_set = config_branch_prediction(0);
-		usb_copy = *(usb_copy_func_t *)
-				EXYNOS_COPY_USB_FNPTR_ADDR;
+		usb_copy = get_irom_func(USB_INDEX);
 		usb_copy();
 		config_branch_prediction(is_cr_z_set);
 		break;
@@ -117,5 +156,4 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	while (1)
 		;
 }
-
 void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S
index 7a1ea98..31e0e2e 100644
--- a/board/samsung/smdkv310/lowlevel_init.S
+++ b/board/samsung/smdkv310/lowlevel_init.S
@@ -85,12 +85,14 @@ lowlevel_init:
 1:
 	/* for UART */
 	bl uart_asm_init
+	bl arch_cpu_init
 	bl tzpc_init
 	pop	{pc}
 
 wakeup_reset:
 	bl system_clock_init
 	bl mem_ctrl_asm_init
+	bl arch_cpu_init
 	bl tzpc_init
 
 exit_wakeup:
@@ -410,61 +412,3 @@ uart_asm_init:
 	nop
 	nop
 	nop
-
-/* Setting TZPC[TrustZone Protection Controller] */
-tzpc_init:
-	ldr	r0, =0x10110000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	ldr	r0, =0x10120000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	ldr	r0, =0x10130000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	ldr	r0, =0x10140000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	ldr	r0, =0x10150000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	ldr	r0, =0x10160000
-	mov	r1, #0x0
-	str	r1, [r0]
-	mov	r1, #0xff
-	str	r1, [r0, #0x0804]
-	str	r1, [r0, #0x0810]
-	str	r1, [r0, #0x081C]
-	str	r1, [r0, #0x0828]
-
-	mov	pc, lr
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 638cc4d..fdbe26c 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -38,9 +38,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define MII_MODE_ENABLE		0x0
@@ -126,28 +123,7 @@ static int read_eeprom(void)
 	return 0;
 }
 
-/* UART Defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET		(0x1 << 1)
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
-	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-	/*
-	 * Unlock the RTC's registers.  For more details please see the
-	 * RTC_SS section of the TRM.  In order to unlock we need to
-	 * write these specific values (keys) in this order.
-	 */
-	writel(0x83e70b13, &rtc->kick0r);
-	writel(0x95a4f1e0, &rtc->kick1r);
-
-	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
-	writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr2_data = {
 	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
 			  (MT47H128M16RT25E_RD_DQS<<20) |
@@ -339,9 +315,6 @@ void s_init(void)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
 
-	/* UART softreset */
-	u32 regVal;
-
 #ifdef CONFIG_SERIAL1
 	enable_uart0_pin_mux();
 #endif /* CONFIG_SERIAL1 */
@@ -361,17 +334,7 @@ void s_init(void)
 	enable_uart5_pin_mux();
 #endif /* CONFIG_SERIAL6 */
 
-	regVal = readl(&uart_base->uartsyscfg);
-	regVal |= UART_RESET;
-	writel(regVal, &uart_base->uartsyscfg);
-	while ((readl(&uart_base->uartsyssts) &
-		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-		;
-
-	/* Disable smart idle */
-	regVal = readl(&uart_base->uartsyscfg);
-	regVal |= UART_SMART_IDLE_EN;
-	writel(regVal, &uart_base->uartsyscfg);
+	uart_soft_reset();
 
 	gd = &gdata;
 
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 90ae29e..1da5b35 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -37,6 +37,11 @@
 #endif
 
 #define PANDA_ULPI_PHY_TYPE_GPIO       182
+#define PANDA_BOARD_ID_1_GPIO          101
+#define PANDA_ES_BOARD_ID_1_GPIO        48
+#define PANDA_BOARD_ID_2_GPIO          171
+#define PANDA_ES_BOARD_ID_3_GPIO         3
+#define PANDA_ES_BOARD_ID_4_GPIO         2
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -66,6 +71,73 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+/*
+* Routine: get_board_revision
+* Description: Detect if we are running on a panda revision A1-A6,
+*              or an ES panda board. This can be done by reading
+*              the level of GPIOs and checking the processor revisions.
+*              This should result in:
+*			Panda 4430:
+*              GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
+*              GPIO171, GPIO101, GPIO182: 1 0 1 => A6
+*			Panda ES:
+*              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
+*              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
+*/
+int get_board_revision(void)
+{
+	int board_id0, board_id1, board_id2;
+	int board_id3, board_id4;
+	int board_id;
+
+	int processor_rev = omap_revision();
+
+	/* Setup the mux for the common board ID pins (gpio 171 and 182) */
+	writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
+	writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
+
+	board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
+	board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
+
+	if ((processor_rev >= OMAP4460_ES1_0 &&
+	     processor_rev <= OMAP4460_ES1_1)) {
+		/*
+		 * Setup the mux for the ES specific board ID pins (gpio 101,
+		 * 2 and 3.
+		 */
+		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+				GPMC_A24);
+		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+				UNIPRO_RY0);
+		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+				UNIPRO_RX1);
+
+		board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
+		board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
+		board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+		setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
+#endif
+		board_id = ((board_id4 << 4) | (board_id3 << 3) |
+			(board_id2 << 2) | (board_id1 << 1) | (board_id0));
+	} else {
+		/* Setup the mux for the Ax specific board ID pins (gpio 101) */
+		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+				FREF_CLK2_OUT);
+
+		board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
+		board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+		if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
+			setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4"));
+#endif
+	}
+
+	return board_id;
+}
+
 /**
  * @brief misc_init_r - Configure Panda board specific configurations
  * such as power configurations, ethernet initialization as phase2 of
@@ -82,11 +154,7 @@ int misc_init_r(void)
 	if (omap_revision() == OMAP4430_ES1_0)
 		return 0;
 
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	if (omap_revision() >= OMAP4460_ES1_0 ||
-		omap_revision() <= OMAP4460_ES1_1)
-		setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
-#endif
+	get_board_revision();
 
 	gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
 	phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
@@ -106,7 +174,7 @@ int misc_init_r(void)
 		auxclk |= AUXCLK_ENABLE_MASK;
 
 		writel(auxclk, &scrm->auxclk3);
-       } else {
+	} else {
 		/* ULPI PHY supplied by auxclk1 derived from PER dpll */
 		debug("ULPI PHY supplied by auxclk1\n");
 
@@ -151,9 +219,9 @@ void set_muxconf_regs_essential(void)
 
 	if (omap_revision() >= OMAP4460_ES1_0)
 		do_set_mux((*ctrl)->control_padconf_wkup_base,
-				 wkup_padconf_array_essential_4460,
-				 sizeof(wkup_padconf_array_essential_4460) /
-				 sizeof(struct pad_conf_entry));
+			   wkup_padconf_array_essential_4460,
+			   sizeof(wkup_padconf_array_essential_4460) /
+			   sizeof(struct pad_conf_entry));
 }
 
 void set_muxconf_regs_non_essential(void)
@@ -165,14 +233,14 @@ void set_muxconf_regs_non_essential(void)
 
 	if (omap_revision() < OMAP4460_ES1_0)
 		do_set_mux((*ctrl)->control_padconf_core_base,
-				core_padconf_array_non_essential_4430,
-				sizeof(core_padconf_array_non_essential_4430) /
-				sizeof(struct pad_conf_entry));
+			   core_padconf_array_non_essential_4430,
+			   sizeof(core_padconf_array_non_essential_4430) /
+			   sizeof(struct pad_conf_entry));
 	else
 		do_set_mux((*ctrl)->control_padconf_core_base,
-				core_padconf_array_non_essential_4460,
-				sizeof(core_padconf_array_non_essential_4460) /
-				sizeof(struct pad_conf_entry));
+			   core_padconf_array_non_essential_4460,
+			   sizeof(core_padconf_array_non_essential_4460) /
+			   sizeof(struct pad_conf_entry));
 
 	do_set_mux((*ctrl)->control_padconf_wkup_base,
 		   wkup_padconf_array_non_essential,
@@ -181,9 +249,9 @@ void set_muxconf_regs_non_essential(void)
 
 	if (omap_revision() < OMAP4460_ES1_0)
 		do_set_mux((*ctrl)->control_padconf_wkup_base,
-				wkup_padconf_array_non_essential_4430,
-				sizeof(wkup_padconf_array_non_essential_4430) /
-				sizeof(struct pad_conf_entry));
+			   wkup_padconf_array_non_essential_4430,
+			   sizeof(wkup_padconf_array_non_essential_4430) /
+			   sizeof(struct pad_conf_entry));
 }
 
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 4759b16..6ad3dd8 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -37,49 +37,16 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SPL_BUILD
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 #endif
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
 /* UART Defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET		(0x1 << 1)
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
-	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-	/*
-	 * Unlock the RTC's registers.  For more details please see the
-	 * RTC_SS section of the TRM.  In order to unlock we need to
-	 * write these specific values (keys) in this order.
-	 */
-	writel(0x83e70b13, &rtc->kick0r);
-	writel(0x95a4f1e0, &rtc->kick1r);
-
-	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
-	writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static void uart_enable(void)
 {
-	u32 regVal;
-
 	/* UART softreset */
-	regVal = readl(&uart_base->uartsyscfg);
-	regVal |= UART_RESET;
-	writel(regVal, &uart_base->uartsyscfg);
-	while ((readl(&uart_base->uartsyssts) &
-		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-		;
-
-	/* Disable smart idle */
-	regVal = readl(&uart_base->uartsyscfg);
-	regVal |= UART_SMART_IDLE_EN;
-	writel(regVal, &uart_base->uartsyscfg);
+	uart_soft_reset();
 }
 
 static void wdt_disable(void)
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
index 61d1154..1a3ef92 100644
--- a/board/vpac270/u-boot-spl.lds
+++ b/board/vpac270/u-boot-spl.lds
@@ -67,11 +67,6 @@ SECTIONS
 		__rel_dyn_end = .;
 	}
 
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
 	. = ALIGN(0x800);
 
 	_end = .;
@@ -84,6 +79,7 @@ SECTIONS
 	}
 
 	/DISCARD/ : { *(.bss*) }
+	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }
 	/DISCARD/ : { *(.dynsym*) }
 	/DISCARD/ : { *(.dynamic*) }
diff --git a/boards.cfg b/boards.cfg
index 1e598cb..c0c4282 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -831,6 +831,7 @@ P1022DS_36BIT_SPIFLASH       powerpc     mpc85xx     p1022ds             freesca
 P1022DS_SDCARD               powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:SDCARD
 P1022DS_36BIT_SDCARD         powerpc     mpc85xx     p1022ds             freescale	-	    P1022DS:36BIT,SDCARD
 P1022DS_36BIT                powerpc     mpc85xx     p1022ds             freescale      -           P1022DS:36BIT
+P1023RDB                     powerpc     mpc85xx     p1023rdb            freescale      -           P1023RDB
 P1023RDS                     powerpc     mpc85xx     p1023rds            freescale      -           P1023RDS
 P1023RDS_NAND                powerpc     mpc85xx     p1023rds            freescale      -           P1023RDS:NAND
 P1024RDB                     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1024RDB
@@ -900,8 +901,13 @@ P5040DS_NAND		     powerpc     mpc85xx     corenet_ds          freescale      -
 P5040DS_SDCARD		     powerpc     mpc85xx     corenet_ds          freescale      -           P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P5040DS_SPIFLASH	     powerpc     mpc85xx     corenet_ds          freescale      -           P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 BSC9131RDB_SPIFLASH          powerpc     mpc85xx     bsc9131rdb          freescale      -           BSC9131RDB:BSC9131RDB,SPIFLASH
+BSC9131RDB_SPIFLASH_SYSCLK100 powerpc     mpc85xx     bsc9131rdb          freescale      -           BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100
+BSC9131RDB_NAND              powerpc     mpc85xx     bsc9131rdb          freescale      -           BSC9131RDB:BSC9131RDB,NAND
+BSC9131RDB_NAND_SYSCLK100    powerpc     mpc85xx     bsc9131rdb          freescale      -           BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100
 BSC9132QDS_NOR_DDRCLK100     powerpc     mpc85xx     bsc9132qds          freescale      -           BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100
 BSC9132QDS_NOR_DDRCLK133     powerpc     mpc85xx     bsc9132qds          freescale      -           BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133
+BSC9132QDS_NAND_DDRCLK100    powerpc     mpc85xx     bsc9132qds          freescale      -           BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100
+BSC9132QDS_NAND_DDRCLK133    powerpc     mpc85xx     bsc9132qds          freescale      -           BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133
 BSC9132QDS_SDCARD_DDRCLK100  powerpc     mpc85xx     bsc9132qds          freescale      -           BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100
 BSC9132QDS_SDCARD_DDRCLK133  powerpc     mpc85xx     bsc9132qds          freescale      -           BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133
 BSC9132QDS_SPIFLASH_DDRCLK100 powerpc    mpc85xx     bsc9132qds          freescale      -           BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100
@@ -912,12 +918,14 @@ stxssa_4M                    powerpc     mpc85xx     stxssa              stx
 T4240QDS                     powerpc     mpc85xx     t4qds               freescale      -           T4240QDS:PPC_T4240
 T4240QDS_SDCARD              powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 T4240QDS_SPIFLASH            powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+T4240QDS_SRIO_PCIE_BOOT	     powerpc     mpc85xx     t4qds               freescale      -           T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 T4160QDS                     powerpc     mpc85xx     t4qds               freescale      -           T4240QDS:PPC_T4160
 T4160QDS_SDCARD              powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 T4160QDS_SPIFLASH            powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
 B4860QDS                     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4860
 B4860QDS_NAND		     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 B4860QDS_SPIFLASH            powerpc     mpc85xx     b4860qds            freescale	-           B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+B4860QDS_SRIO_PCIE_BOOT	     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 B4420QDS                     powerpc     mpc85xx     b4860qds            freescale	-	    B4860QDS:PPC_B4420
 B4420QDS_NAND		     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 B4420QDS_SPIFLASH            powerpc     mpc85xx     b4860qds            freescale	-           B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
diff --git a/common/Makefile b/common/Makefile
index 3ba4316..3581603 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -44,13 +44,11 @@ COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
 COBJS-y += cmd_boot.o
 COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o
 COBJS-y += cmd_help.o
-COBJS-y += cmd_nvedit.o
 COBJS-y += cmd_version.o
 
 # environment
 COBJS-y += env_attr.o
 COBJS-y += env_callback.o
-COBJS-y += env_common.o
 COBJS-y += env_flags.o
 COBJS-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
 COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
@@ -191,14 +189,6 @@ COBJS-$(CONFIG_CMD_ZIP) += cmd_zip.o
 COBJS-$(CONFIG_CMD_ZFS) += cmd_zfs.o
 
 # others
-ifdef CONFIG_DDR_SPD
-SPD := y
-endif
-ifdef CONFIG_SPD_EEPROM
-SPD := y
-endif
-COBJS-$(SPD) += ddr_spd.o
-COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
 COBJS-$(CONFIG_BOOTSTAGE) += bootstage.o
 COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
 COBJS-y += flash.o
@@ -216,18 +206,36 @@ COBJS-$(CONFIG_CMD_GPT) += cmd_gpt.o
 endif
 
 ifdef CONFIG_SPL_BUILD
-COBJS-y += cmd_nvedit.o
-COBJS-y += env_common.o
 COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += cmd_nvedit.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_attr.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_callback.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_common.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_flags.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
+# environment
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
+ifneq ($(CONFIG_SPL_NET_SUPPORT),y)
+COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
+COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
+COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
+COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
+else
+COBJS-y += env_nowhere.o
+endif
 endif
+# core command
+COBJS-y += cmd_nvedit.o
+#environment
+COBJS-y += env_common.o
+#others
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+COBJS-$(SPD) += ddr_spd.o
+COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
 COBJS-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
 COBJS-y += console.o
 COBJS-y += dlmalloc.o
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 7d82469..5f1ed43 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -147,6 +147,36 @@ U_BOOT_CMD(
 	"- display info of the current MMC device"
 );
 
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+static int boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+{
+	int err;
+	err = mmc_boot_part_access(mmc, ack, part_num, access);
+
+	if ((err == 0) && (access != 0)) {
+		printf("\t\t\t!!!Notice!!!\n");
+
+		printf("!You must close EMMC boot Partition");
+		printf("after all images are written\n");
+
+		printf("!EMMC boot partition has continuity");
+		printf("at image writing time.\n");
+
+		printf("!So, do not close the boot partition");
+		printf("before all images are written.\n");
+		return 0;
+	} else if ((err == 0) && (access == 0))
+		return 0;
+	else if ((err != 0) && (access != 0)) {
+		printf("EMMC boot partition-%d OPEN Failed.\n", part_num);
+		return 1;
+	} else {
+		printf("EMMC boot partition-%d CLOSE Failed.\n", part_num);
+		return 1;
+	}
+}
+#endif
+
 static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	enum mmc_state state;
@@ -258,8 +288,74 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				curr_device, mmc->part_num);
 
 		return 0;
-	}
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	} else if ((strcmp(argv[1], "open") == 0) ||
+			(strcmp(argv[1], "close") == 0)) {
+		int dev;
+		struct mmc *mmc;
+		u8 part_num, access = 0;
+
+		if (argc == 4) {
+			dev = simple_strtoul(argv[2], NULL, 10);
+			part_num = simple_strtoul(argv[3], NULL, 10);
+		} else {
+			return CMD_RET_USAGE;
+		}
+
+		mmc = find_mmc_device(dev);
+		if (!mmc) {
+			printf("no mmc device at slot %x\n", dev);
+			return 1;
+		}
 
+		if (IS_SD(mmc)) {
+			printf("SD device cannot be opened/closed\n");
+			return 1;
+		}
+
+		if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) {
+			printf("Invalid boot partition number:\n");
+			printf("Boot partition number cannot be <= 0\n");
+			printf("EMMC44 supports only 2 boot partitions\n");
+			return 1;
+		}
+
+		if (strcmp(argv[1], "open") == 0)
+			access = part_num; /* enable R/W access to boot part*/
+		else
+			access = 0; /* No access to boot partition */
+
+		/* acknowledge to be sent during boot operation */
+		return boot_part_access(mmc, 1, part_num, access);
+
+	} else if (strcmp(argv[1], "bootpart") == 0) {
+		int dev;
+		dev = simple_strtoul(argv[2], NULL, 10);
+
+		u32 bootsize = simple_strtoul(argv[3], NULL, 10);
+		u32 rpmbsize = simple_strtoul(argv[4], NULL, 10);
+		struct mmc *mmc = find_mmc_device(dev);
+		if (!mmc) {
+			printf("no mmc device at slot %x\n", dev);
+			return 1;
+		}
+
+		if (IS_SD(mmc)) {
+			printf("It is not a EMMC device\n");
+			return 1;
+		}
+
+		if (0 == mmc_boot_partition_size_change(mmc,
+							bootsize, rpmbsize)) {
+			printf("EMMC boot partition Size %d MB\n", bootsize);
+			printf("EMMC RPMB partition Size %d MB\n", rpmbsize);
+			return 0;
+		} else {
+			printf("EMMC boot partition Size change Failed.\n");
+			return 1;
+		}
+#endif /* CONFIG_SUPPORT_EMMC_BOOT */
+	}
 	state = MMC_INVALID;
 	if (argc == 5 && strcmp(argv[1], "read") == 0)
 		state = MMC_READ;
@@ -334,5 +430,14 @@ U_BOOT_CMD(
 	"mmc rescan\n"
 	"mmc part - lists available partition on current mmc device\n"
 	"mmc dev [dev] [part] - show or set current mmc device [partition]\n"
-	"mmc list - lists available devices");
+	"mmc list - lists available devices\n"
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+	"mmc open <dev> <boot_partition>\n"
+	" - Enable boot_part for booting and enable R/W access of boot_part\n"
+	"mmc close <dev> <boot_partition>\n"
+	" - Enable boot_part for booting and disable access to boot_part\n"
+	"mmc bootpart <device num> <boot part size MB> <RPMB part size MB>\n"
+	" - change sizes of boot and RPMB partions of specified device\n"
 #endif
+	);
+#endif /* !CONFIG_GENERIC_MMC */
diff --git a/doc/README.srio-pcie-boot-corenet b/doc/README.srio-pcie-boot-corenet
index cd7e7ee..2b1f76b 100644
--- a/doc/README.srio-pcie-boot-corenet
+++ b/doc/README.srio-pcie-boot-corenet
@@ -21,13 +21,13 @@ Environment of the SRIO or PCIE boot:
 	e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
 	   the boot location to SRIO or PCIE, and holdoff all the cores.
 
-	----------        -----------             -----------
-	|		  |       |         |             |         |
-	|		  |       |         |             |         |
+	-----------       -----------             -----------
+	|         |       |         |             |         |
+	|         |       |         |             |         |
 	| NorFlash|<----->| Master  |SRIO or PCIE |  Slave  |<---->[EEPROM]
-	|		  |       |         |<===========>|         |
-	|		  |       |         |             |         |
-	----------        -----------             -----------
+	|         |       |         |<===========>|         |
+	|         |       |         |             |         |
+	-----------       -----------             -----------
 
 The example based on P4080DS platform:
 	Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
@@ -87,26 +87,32 @@ How to use this feature:
 	   Please refer to the examples given above.
 
 	2. U-Boot image's compilation.
-		For master, U-Boot image should be generated normally.
+	   For master, U-Boot image should be generated normally.
 
-		For example, master U-Boot image used on P4080DS should be compiled with
+	   For example, master U-Boot image used on P4080DS should be compiled with
 
 				make P4080DS_config.
 
-		For slave, U-Boot image should be generated specifically by
+	   For slave, U-Boot image should be generated specifically by
 
 				make xxxx_SRIO_PCIE_BOOT_config.
 
-		For example, slave U-Boot image used on P4080DS should be compiled with
+	   For example, slave U-Boot image used on P4080DS should be compiled with
 
 				make P4080DS_SRIO_PCIE_BOOT_config.
 
 	3. Necessary modifications based on a specific environment.
-		For a specific environment, the addresses of the slave's U-Boot image,
-		UCode, ENV stored in master's NorFlash, and any other configurations
-		can be modified in the file:
-					include/configs/corenet_ds.h.
+	   For a specific environment, the addresses of the slave's U-Boot image,
+	   UCode, ENV stored in master's NorFlash, and any other configurations
+	   can be modified in the file:
+				include/configs/corenet_ds.h.
 
 	4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
 	   or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
 	   perform the role as a master for boot from SRIO or PCIE.
+
+NOTE: When the Slave's ENV parameters are stored in Master's NorFlash,
+      it can fetch them through PCIE or SRIO interface. But the ENV
+      parameters can not be modified by "saveenv" or other commands under
+      the Slave's u-boot environment, because the Slave can not erase,
+      write Master's NorFlash by PCIE or SRIO link.
diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt b/doc/device-tree-bindings/exynos/dwmmc.txt
new file mode 100644
index 0000000..566da3b
--- /dev/null
+++ b/doc/device-tree-bindings/exynos/dwmmc.txt
@@ -0,0 +1,54 @@
+* Exynos 5250 DWC_mobile_storage
+
+The Exynos 5250 provides DWC_mobile_storage interface which supports
+. Embedded Multimedia Cards (EMMC-version 4.5)
+. Secure Digital memory (SD mem-version 2.0)
+. Secure Digital I/O (SDIO-version 3.0)
+. Consumer Electronics Advanced Transport Architecture (CE-ATA-version 1.1)
+
+The Exynos 5250 DWC_mobile_storage provides four channels.
+SOC specific and Board specific properties are channel specific.
+
+Required SoC Specific Properties:
+
+- compatible: should be
+	- samsung,exynos5250-dwmmc: for exynos5250 platforms
+
+- reg: physical base address of the controller and length of memory mapped
+	region.
+
+- interrupts: The interrupt number to the cpu.
+
+Required Board Specific Properties:
+
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- samsung,bus-width: The width of the bus used to interface the devices
+	supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO).
+	. Typically the bus width is 4 or 8.
+- samsung,timing: The timing values to be written into the
+	Drv/sample clock selection register of corresponding channel.
+	. It is comprised of 3 values corresponding to the 3 fileds
+	  'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register.
+	. SelClk_sample: Select sample clock among 8 shifted clocks.
+	. SelClk_drv: Select drv clock among 8 shifted clocks.
+	. DIVRATIO: Clock Divide ratio select.
+	. The above 3 values are used by the clock phase shifter.
+
+Example:
+
+mmc@12200000 {
+	samsung,bus-width = <8>;
+	samsung,timing = <1 3 3>;
+	samsung,removable = <1>;
+}
+In the above example,
+	. The bus width is 8
+	. Timing is comprised of 3 values as explained below
+		1 - SelClk_sample
+		3 - SelClk_drv
+		3 - DIVRATIO
+	. The 'removable' flag indicates whether the the particilar device
+	  cannot be removed (always present) or it is a removable device.
+		1 - Indicates that the device is removable.
+		0 - Indicates that the device cannot be removed.
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 4070d4e..5da20ed 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -129,13 +129,13 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	unsigned int timeout = 100000;
 	u32 retry = 10000;
 	u32 mask, ctrl;
+	ulong start = get_timer(0);
 
 	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
-		if (timeout == 0) {
+		if (get_timer(start) > timeout) {
 			printf("Timeout on data busy\n");
 			return TIMEOUT;
 		}
-		timeout--;
 	}
 
 	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
@@ -143,7 +143,6 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 	if (data)
 		dwmci_prepare_data(host, data);
 
-
 	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 
 	if (data)
@@ -231,9 +230,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 	int timeout = 10000;
 	unsigned long sclk;
 
-	if (freq == host->clock)
+	if ((freq == host->clock) || (freq == 0))
 		return 0;
-
 	/*
 	 * If host->mmc_clk didn't define,
 	 * then assume that host->bus_hz is source clock value.
@@ -314,7 +312,7 @@ static void dwmci_set_ios(struct mmc *mmc)
 static int dwmci_init(struct mmc *mmc)
 {
 	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
-	u32 fifo_size, fifoth_val;
+	u32 fifo_size;
 
 	dwmci_writel(host, DWMCI_PWREN, 1);
 
@@ -323,6 +321,9 @@ static int dwmci_init(struct mmc *mmc)
 		return -1;
 	}
 
+	/* Enumerate at 400KHz */
+	dwmci_setup_bus(host, mmc->f_min);
+
 	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 	dwmci_writel(host, DWMCI_INTMASK, 0);
 
@@ -331,13 +332,13 @@ static int dwmci_init(struct mmc *mmc)
 	dwmci_writel(host, DWMCI_IDINTEN, 0);
 	dwmci_writel(host, DWMCI_BMOD, 1);
 
-	fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
-	if (host->fifoth_val)
-		fifoth_val = host->fifoth_val;
-	else
-		fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
-			TX_WMARK(fifo_size/2);
-	dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
+	if (!host->fifoth_val) {
+		fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+		fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
+		host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
+			TX_WMARK(fifo_size / 2);
+	}
+	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 
 	dwmci_writel(host, DWMCI_CLKENA, 0);
 	dwmci_writel(host, DWMCI_CLKSRC, 0);
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 72a31b7..4238dd9 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -19,39 +19,146 @@
  */
 
 #include <common.h>
-#include <malloc.h>
 #include <dwmmc.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <malloc.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/pinmux.h>
 
-static char *EXYNOS_NAME = "EXYNOS DWMMC";
+#define	DWMMC_MAX_CH_NUM		4
+#define	DWMMC_MAX_FREQ			52000000
+#define	DWMMC_MIN_FREQ			400000
+#define	DWMMC_MMC0_CLKSEL_VAL		0x03030001
+#define	DWMMC_MMC2_CLKSEL_VAL		0x03020001
 
+/*
+ * Function used as callback function to initialise the
+ * CLKSEL register for every mmc channel.
+ */
 static void exynos_dwmci_clksel(struct dwmci_host *host)
 {
-	u32 val;
-	val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
-		DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
+	dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
+}
 
-	dwmci_writel(host, DWMCI_CLKSEL, val);
+unsigned int exynos_dwmci_get_clk(int dev_index)
+{
+	return get_mmc_clk(dev_index);
 }
 
-int exynos_dwmci_init(u32 regbase, int bus_width, int index)
+/*
+ * This function adds the mmc channel to be registered with mmc core.
+ * index -	mmc channel number.
+ * regbase -	register base address of mmc channel specified in 'index'.
+ * bus_width -	operating bus width of mmc channel specified in 'index'.
+ * clksel -	value to be written into CLKSEL register in case of FDT.
+ *		NULL in case od non-FDT.
+ */
+int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
 {
 	struct dwmci_host *host = NULL;
+	unsigned int div;
+	unsigned long freq, sclk;
 	host = malloc(sizeof(struct dwmci_host));
 	if (!host) {
 		printf("dwmci_host malloc fail!\n");
 		return 1;
 	}
+	/* request mmc clock vlaue of 52MHz.  */
+	freq = 52000000;
+	sclk = get_mmc_clk(index);
+	div = DIV_ROUND_UP(sclk, freq);
+	/* set the clock divisor for mmc */
+	set_mmc_clk(index, div);
 
-	host->name = EXYNOS_NAME;
+	host->name = "EXYNOS DWMMC";
 	host->ioaddr = (void *)regbase;
 	host->buswidth = bus_width;
+
+	if (clksel) {
+		host->clksel_val = clksel;
+	} else {
+		if (0 == index)
+			host->clksel_val = DWMMC_MMC0_CLKSEL_VAL;
+		if (2 == index)
+			host->clksel_val = DWMMC_MMC2_CLKSEL_VAL;
+	}
+
 	host->clksel = exynos_dwmci_clksel;
 	host->dev_index = index;
+	host->mmc_clk = exynos_dwmci_get_clk;
+	/* Add the mmc channel to be registered with mmc core */
+	if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
+		debug("dwmmc%d registration failed\n", index);
+		return -1;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_OF_CONTROL
+int exynos_dwmmc_init(const void *blob)
+{
+	int index, bus_width;
+	int node_list[DWMMC_MAX_CH_NUM];
+	int err = 0, dev_id, flag, count, i;
+	u32 clksel_val, base, timing[3];
+
+	count = fdtdec_find_aliases_for_id(blob, "mmc",
+				COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
+				DWMMC_MAX_CH_NUM);
+
+	for (i = 0; i < count; i++) {
+		int node = node_list[i];
+
+		if (node <= 0)
+			continue;
 
-	add_dwmci(host, 52000000, 400000);
+		/* Extract device id for each mmc channel */
+		dev_id = pinmux_decode_periph_id(blob, node);
 
+		/* Get the bus width from the device node */
+		bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
+		if (bus_width <= 0) {
+			debug("DWMMC: Can't get bus-width\n");
+			return -1;
+		}
+		if (8 == bus_width)
+			flag = PINMUX_FLAG_8BIT_MODE;
+		else
+			flag = PINMUX_FLAG_NONE;
+
+		/* config pinmux for each mmc channel */
+		err = exynos_pinmux_config(dev_id, flag);
+		if (err) {
+			debug("DWMMC not configured\n");
+			return err;
+		}
+
+		index = dev_id - PERIPH_ID_SDMMC0;
+
+		/* Get the base address from the device node */
+		base = fdtdec_get_addr(blob, node, "reg");
+		if (!base) {
+			debug("DWMMC: Can't get base address\n");
+			return -1;
+		}
+		/* Extract the timing info from the node */
+		err = fdtdec_get_int_array(blob, node, "samsung,timing",
+					timing, 3);
+		if (err) {
+			debug("Can't get sdr-timings for divider\n");
+			return -1;
+		}
+
+		clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
+				DWMCI_SET_DRV_CLK(timing[1]) |
+				DWMCI_SET_DIV_RATIO(timing[2]));
+		/* Initialise each mmc channel */
+		err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
+		if (err)
+			debug("dwmmc Channel-%d init failed\n", index);
+	}
 	return 0;
 }
-
+#endif
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index e6a296a..83d2df7 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1503,3 +1503,137 @@ int mmc_initialize(bd_t *bis)
 	do_preinit();
 	return 0;
 }
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+/*
+ * This function changes the size of boot partition and the size of rpmb
+ * partition present on EMMC devices.
+ *
+ * Input Parameters:
+ * struct *mmc: pointer for the mmc device strcuture
+ * bootsize: size of boot partition
+ * rpmbsize: size of rpmb partition
+ *
+ * Returns 0 on success.
+ */
+
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+				unsigned long rpmbsize)
+{
+	int err;
+	struct mmc_cmd cmd;
+
+	/* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = MMC_CMD62_ARG1;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
+		return err;
+	}
+
+	/* Boot partition changing mode */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = MMC_CMD62_ARG2;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
+		return err;
+	}
+	/* boot partition size is multiple of 128KB */
+	bootsize = (bootsize * 1024) / 128;
+
+	/* Arg: boot partition size */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = bootsize;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
+		return err;
+	}
+	/* RPMB partition size is multiple of 128KB */
+	rpmbsize = (rpmbsize * 1024) / 128;
+	/* Arg: RPMB partition size */
+	cmd.cmdidx = MMC_CMD_RES_MAN;
+	cmd.resp_type = MMC_RSP_R1b;
+	cmd.cmdarg = rpmbsize;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
+		return err;
+	}
+	return 0;
+}
+
+/*
+ * This function shall form and send the commands to open / close the
+ * boot partition specified by user.
+ *
+ * Input Parameters:
+ * ack: 0x0 - No boot acknowledge sent (default)
+ *	0x1 - Boot acknowledge sent during boot operation
+ * part_num: User selects boot data that will be sent to master
+ *	0x0 - Device not boot enabled (default)
+ *	0x1 - Boot partition 1 enabled for boot
+ *	0x2 - Boot partition 2 enabled for boot
+ * access: User selects partitions to access
+ *	0x0 : No access to boot partition (default)
+ *	0x1 : R/W boot partition 1
+ *	0x2 : R/W boot partition 2
+ *	0x3 : R/W Replay Protected Memory Block (RPMB)
+ *
+ * Returns 0 on success.
+ */
+int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
+{
+	int err;
+	struct mmc_cmd cmd;
+
+	/* Boot ack enable, boot partition enable , boot partition access */
+	cmd.cmdidx = MMC_CMD_SWITCH;
+	cmd.resp_type = MMC_RSP_R1b;
+
+	cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
+			(EXT_CSD_PART_CONF << 16) |
+			((EXT_CSD_BOOT_ACK(ack) |
+			EXT_CSD_BOOT_PART_NUM(part_num) |
+			EXT_CSD_PARTITION_ACCESS(access)) << 8);
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err) {
+		if (access) {
+			debug("mmc boot partition#%d open fail:Error1 = %d\n",
+			      part_num, err);
+		} else {
+			debug("mmc boot partition#%d close fail:Error = %d\n",
+			      part_num, err);
+		}
+		return err;
+	}
+
+	if (access) {
+		/* 4bit transfer mode at booting time. */
+		cmd.cmdidx = MMC_CMD_SWITCH;
+		cmd.resp_type = MMC_RSP_R1b;
+
+		cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
+				(EXT_CSD_BOOT_BUS_WIDTH << 16) |
+				((1 << 0) << 8);
+
+		err = mmc_send_cmd(mmc, &cmd, NULL);
+		if (err) {
+			debug("mmc boot partition#%d open fail:Error2 = %d\n",
+			      part_num, err);
+			return err;
+		}
+	}
+	return 0;
+}
+#endif
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8821704..bb81e84 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -83,6 +83,7 @@ COBJS-$(CONFIG_NAND_DOCG4) += docg4.o
 else  # minimal SPL drivers
 
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
+COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
 COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
 
 endif # drivers
diff --git a/nand_spl/nand_boot_fsl_ifc.c b/drivers/mtd/nand/fsl_ifc_spl.c
similarity index 88%
rename from nand_spl/nand_boot_fsl_ifc.c
rename to drivers/mtd/nand/fsl_ifc_spl.c
index 44972c5..8537c4c 100644
--- a/nand_spl/nand_boot_fsl_ifc.c
+++ b/drivers/mtd/nand/fsl_ifc_spl.c
@@ -1,5 +1,5 @@
 /*
- * NAND boot for FSL Integrated Flash Controller, NAND Flash Control Machine
+ * NAND boot for Freescale Integrated Flash Controller, NAND FCM
  *
  * Copyright 2011 Freescale Semiconductor, Inc.
  * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
@@ -46,9 +46,9 @@ static inline int check_read_ecc(uchar *buf, u32 *eccstat,
 				 unsigned int bufnum, int page_size)
 {
 	u32 reg = eccstat[bufnum / 4];
-	int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
+	int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
 
-	if (errors == 15) { /* uncorrectable */
+	if (errors == 0xf) { /* uncorrectable */
 		/* Blank pages fail hw ECC checks */
 		if (is_blank(buf, page_size))
 			return 1;
@@ -123,30 +123,17 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 	csor = CONFIG_SYS_NAND_CSOR;
 	cspr = CONFIG_SYS_NAND_CSPR;
 
-	if (!(csor & CSOR_NAND_ECC_DEC_EN)) {
-		/* soft ECC in SPL is unimplemented */
-		puts("WARNING: soft ECC not checked in SPL\n");
-	} else {
-		u32 hwcsor;
-
-		/* make sure board is configured with ECC on boot */
-		hwcsor = in_be32(&ifc->csor_cs[0].csor);
-		if (!(hwcsor & CSOR_NAND_ECC_DEC_EN))
-			puts("WARNING: ECC not checked in SPL, "
-				"check board cfg\n");
-	}
-
 	port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
 
 	if (csor & CSOR_NAND_PGS_4K) {
 		page_size = 4096;
-		bufnum_mask = 1;
+		bufnum_mask = 0x1;
 	} else if (csor & CSOR_NAND_PGS_2K) {
 		page_size = 2048;
-		bufnum_mask = 3;
+		bufnum_mask = 0x3;
 	} else {
 		page_size = 512;
-		bufnum_mask = 15;
+		bufnum_mask = 0xf;
 
 		if (port_size == 8)
 			bad_marker = 5;
@@ -174,8 +161,8 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
 
 		out_be32(&ifc->ifc_nand.nand_fcr0,
-			(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
-			(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
+			 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
+			 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 	} else {
 		out_be32(&ifc->ifc_nand.nand_fir0,
 			 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
@@ -185,7 +172,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 		out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
 
 		out_be32(&ifc->ifc_nand.nand_fcr0,
-			NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
+			 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 	}
 
 	/* Program FBCR = 0 for full page read */
@@ -206,7 +193,7 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 			out_be32(&ifc->ifc_nand.col0, 0);
 			/* start read */
 			out_be32(&ifc->ifc_nand.nandseq_strt,
-				IFC_NAND_SEQ_STRT_FIR_STRT);
+				 IFC_NAND_SEQ_STRT_FIR_STRT);
 
 			/* wait for read to complete */
 			nand_wait(&buf[sram_addr], bufnum, page_size);
@@ -241,7 +228,6 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
 void nand_boot(void)
 {
 	__attribute__((noreturn)) void (*uboot)(void);
-
 	/*
 	 * Load U-Boot image from NAND into RAM
 	 */
@@ -257,15 +243,16 @@ void nand_boot(void)
 		  (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 #endif
 #endif
-
 	/*
 	 * Jump to U-Boot image
 	 */
+#ifdef CONFIG_SPL_FLUSH_IMAGE
 	/*
 	 * Clean d-cache and invalidate i-cache, to
 	 * make sure that no stale data is executed.
 	 */
 	flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+#endif
 	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 	uboot();
 }
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 90f8392..ecbb210 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -32,6 +32,7 @@ endif
 COBJS-$(CONFIG_SPI_FLASH)	+= spi_flash.o
 COBJS-$(CONFIG_SPI_FLASH_ATMEL)	+= atmel.o
 COBJS-$(CONFIG_SPI_FLASH_EON)	+= eon.o
+COBJS-$(CONFIG_SPI_FLASH_GIGADEVICE)	+= gigadevice.o
 COBJS-$(CONFIG_SPI_FLASH_MACRONIX)	+= macronix.o
 COBJS-$(CONFIG_SPI_FLASH_SPANSION)	+= spansion.o
 COBJS-$(CONFIG_SPI_FLASH_SST)	+= sst.o
diff --git a/drivers/mtd/spi/gigadevice.c b/drivers/mtd/spi/gigadevice.c
new file mode 100644
index 0000000..b5e1ebe
--- /dev/null
+++ b/drivers/mtd/spi/gigadevice.c
@@ -0,0 +1,81 @@
+/*
+ * Gigadevice SPI flash driver
+ * Copyright 2013, Samsung Electronics Co., Ltd.
+ * Author: Banajit Goswami <banajit.g@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+#include "spi_flash_internal.h"
+
+struct gigadevice_spi_flash_params {
+	uint16_t	id;
+	uint16_t	nr_blocks;
+	const char	*name;
+};
+
+static const struct gigadevice_spi_flash_params gigadevice_spi_flash_table[] = {
+	{
+		.id			= 0x6016,
+		.nr_blocks		= 64,
+		.name			= "GD25LQ",
+	},
+	{
+		.id			= 0x4017,
+		.nr_blocks		= 128,
+		.name			= "GD25Q64B",
+	},
+};
+
+struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode)
+{
+	const struct gigadevice_spi_flash_params *params;
+	struct spi_flash *flash;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(gigadevice_spi_flash_table); i++) {
+		params = &gigadevice_spi_flash_table[i];
+		if (params->id == ((idcode[1] << 8) | idcode[2]))
+			break;
+	}
+
+	if (i == ARRAY_SIZE(gigadevice_spi_flash_table)) {
+		debug("SF: Unsupported Gigadevice ID %02x%02x\n",
+				idcode[1], idcode[2]);
+		return NULL;
+	}
+
+	flash = spi_flash_alloc_base(spi, params->name);
+	if (!flash) {
+		debug("SF: Failed to allocate memory\n");
+		return NULL;
+	}
+	/* page_size */
+	flash->page_size = 256;
+	/* sector_size = page_size * pages_per_sector */
+	flash->sector_size = flash->page_size * 16;
+	/* size = sector_size * sector_per_block * number of blocks */
+	flash->size = flash->sector_size * 16 * params->nr_blocks;
+
+	return flash;
+}
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index a468208..6a6fe37 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -458,6 +458,9 @@ static const struct {
 #ifdef CONFIG_SPI_FLASH_EON
 	{ 0, 0x1c, spi_flash_probe_eon, },
 #endif
+#ifdef CONFIG_SPI_FLASH_GIGADEVICE
+	{ 0, 0xc8, spi_flash_probe_gigadevice, },
+#endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX
 	{ 0, 0xc2, spi_flash_probe_macronix, },
 #endif
diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h
index be3c768..af1afa9 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -137,3 +137,4 @@ struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
 struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
 struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
 struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode);
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 77ac1f7..621c899 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
 	return 1;
 }
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 static void fsl_pcie_boot_master(pit_t *pi)
 {
 	/* configure inbound window for slave's u-boot image */
@@ -388,7 +388,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 	/* see if we are a PCIe or PCI controller */
 	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	/* boot from PCIE --master */
 	char *s = getenv("bootmaster");
 	char pcie[6];
@@ -624,7 +624,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 	if (fsl_is_pci_agent(hose)) {
 		fsl_pci_config_unlock(hose);
 		hose->last_busno = hose->first_busno;
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	} else {
 		/* boot from PCIE --master releases slave's core 0 */
 		char *s = getenv("bootmaster");
diff --git a/drivers/power/exynos-tmu.c b/drivers/power/exynos-tmu.c
index d4b3e65..9a093a5 100644
--- a/drivers/power/exynos-tmu.c
+++ b/drivers/power/exynos-tmu.c
@@ -50,15 +50,15 @@
 /* Tmeperature threshold values for various thermal events */
 struct temperature_params {
 	/* minimum value in temperature code range */
-	unsigned int min_val;
+	unsigned min_val;
 	/* maximum value in temperature code range */
-	unsigned int max_val;
+	unsigned max_val;
 	/* temperature threshold to start warning */
-	unsigned int start_warning;
+	unsigned start_warning;
 	/* temperature threshold CPU tripping */
-	unsigned int start_tripping;
+	unsigned start_tripping;
 	/* temperature threshold for HW tripping */
-	unsigned int hardware_tripping;
+	unsigned hardware_tripping;
 };
 
 /* Pre-defined values and thresholds for calibration of current temperature */
@@ -66,25 +66,27 @@ struct tmu_data {
 	/* pre-defined temperature thresholds */
 	struct temperature_params ts;
 	/* pre-defined efuse range minimum value */
-	unsigned int efuse_min_value;
+	unsigned efuse_min_value;
 	/* pre-defined efuse value for temperature calibration */
-	unsigned int efuse_value;
+	unsigned efuse_value;
 	/* pre-defined efuse range maximum value */
-	unsigned int efuse_max_value;
+	unsigned efuse_max_value;
 	/* current temperature sensing slope */
-	unsigned int slope;
+	unsigned slope;
 };
 
 /* TMU device specific details and status */
 struct tmu_info {
 	/* base Address for the TMU */
-	unsigned tmu_base;
+	struct exynos5_tmu_reg *tmu_base;
+	/* mux Address for the TMU */
+	int tmu_mux;
 	/* pre-defined values for calibration and thresholds */
 	struct tmu_data data;
 	/* value required for triminfo_25 calibration */
-	unsigned int te1;
+	unsigned te1;
 	/* value required for triminfo_85 calibration */
-	unsigned int te2;
+	unsigned te2;
 	/* Value for measured data calibration */
 	int dc_value;
 	/* enum value indicating status of the TMU */
@@ -103,17 +105,24 @@ static struct tmu_info gbl_info;
  */
 static int get_cur_temp(struct tmu_info *info)
 {
-	int cur_temp;
-	struct exynos5_tmu_reg *reg = (struct exynos5_tmu_reg *)info->tmu_base;
+	struct exynos5_tmu_reg *reg = info->tmu_base;
+	ulong start;
+	int cur_temp = 0;
 
 	/*
 	 * Temperature code range between min 25 and max 125.
 	 * May run more than once for first call as initial sensing
 	 * has not yet happened.
 	 */
-	do {
-		cur_temp = readl(&reg->current_temp) & 0xff;
-	} while (cur_temp == 0 && info->tmu_state == TMU_STATUS_NORMAL);
+	if (info->tmu_state == TMU_STATUS_NORMAL) {
+		start = get_timer(0);
+		do {
+			cur_temp = readl(&reg->current_temp) & 0xff;
+		} while ((cur_temp == 0) || (get_timer(start) > 100));
+	}
+
+	if (cur_temp == 0)
+		return cur_temp;
 
 	/* Calibrate current temperature */
 	cur_temp = cur_temp - info->te1 + info->dc_value;
@@ -137,23 +146,29 @@ enum tmu_status_t tmu_monitor(int *temp)
 
 	/* Read current temperature of the SOC */
 	cur_temp = get_cur_temp(&gbl_info);
+
+	if (!cur_temp)
+		goto out;
+
 	*temp = cur_temp;
 
 	/* Temperature code lies between min 25 and max 125 */
-	if (cur_temp >= data->ts.start_tripping &&
-			cur_temp <= data->ts.max_val) {
+	if ((cur_temp >= data->ts.start_tripping) &&
+	    (cur_temp <= data->ts.max_val))
 		return TMU_STATUS_TRIPPED;
-	} else if (cur_temp >= data->ts.start_warning) {
+
+	if (cur_temp >= data->ts.start_warning)
 		return TMU_STATUS_WARNING;
-	} else if (cur_temp < data->ts.start_warning &&
-			cur_temp >= data->ts.min_val) {
+
+	if ((cur_temp < data->ts.start_warning) &&
+	    (cur_temp >= data->ts.min_val))
 		return TMU_STATUS_NORMAL;
-	} else {
-		/* Temperature code does not lie between min 25 and max 125 */
-		gbl_info.tmu_state = TMU_STATUS_INIT;
-		debug("EXYNOS_TMU: Thermal reading failed\n");
-		return TMU_STATUS_INIT;
-	}
+
+ out:
+	/* Temperature code does not lie between min 25 and max 125 */
+	gbl_info.tmu_state = TMU_STATUS_INIT;
+	debug("EXYNOS_TMU: Thermal reading failed\n");
+	return TMU_STATUS_INIT;
 }
 
 /*
@@ -166,6 +181,7 @@ enum tmu_status_t tmu_monitor(int *temp)
 static int get_tmu_fdt_values(struct tmu_info *info, const void *blob)
 {
 #ifdef CONFIG_OF_CONTROL
+	fdt_addr_t addr;
 	int node;
 	int error = 0;
 
@@ -183,46 +199,58 @@ static int get_tmu_fdt_values(struct tmu_info *info, const void *blob)
 	 * miscalculation of register values in tmu_setup_parameters
 	 * may result in misleading current temperature.
 	 */
-	info->tmu_base = fdtdec_get_addr(blob, node, "reg");
-	if (info->tmu_base == FDT_ADDR_T_NONE) {
+	addr = fdtdec_get_addr(blob, node, "reg");
+	if (addr == FDT_ADDR_T_NONE) {
 		debug("%s: Missing tmu-base\n", __func__);
 		return -1;
 	}
+	info->tmu_base = (struct exynos5_tmu_reg *)addr;
+
+	/* Optional field. */
+	info->tmu_mux = fdtdec_get_int(blob,
+				node, "samsung,mux", -1);
+	/* Take default value as per the user manual b(110) */
+	if (info->tmu_mux == -1)
+		info->tmu_mux = 0x6;
+
 	info->data.ts.min_val = fdtdec_get_int(blob,
 				node, "samsung,min-temp", -1);
-	error |= info->data.ts.min_val;
+	error |= (info->data.ts.min_val == -1);
 	info->data.ts.max_val = fdtdec_get_int(blob,
 				node, "samsung,max-temp", -1);
-	error |= info->data.ts.max_val;
+	error |= (info->data.ts.max_val == -1);
 	info->data.ts.start_warning = fdtdec_get_int(blob,
 				node, "samsung,start-warning", -1);
-	error |= info->data.ts.start_warning;
+	error |= (info->data.ts.start_warning == -1);
 	info->data.ts.start_tripping = fdtdec_get_int(blob,
 				node, "samsung,start-tripping", -1);
-	error |= info->data.ts.start_tripping;
+	error |= (info->data.ts.start_tripping == -1);
 	info->data.ts.hardware_tripping = fdtdec_get_int(blob,
 				node, "samsung,hw-tripping", -1);
-	error |= info->data.ts.hardware_tripping;
+	error |= (info->data.ts.hardware_tripping == -1);
 	info->data.efuse_min_value = fdtdec_get_int(blob,
 				node, "samsung,efuse-min-value", -1);
-	error |= info->data.efuse_min_value;
+	error |= (info->data.efuse_min_value == -1);
 	info->data.efuse_value = fdtdec_get_int(blob,
 				node, "samsung,efuse-value", -1);
-	error |= info->data.efuse_value;
+	error |= (info->data.efuse_value == -1);
 	info->data.efuse_max_value = fdtdec_get_int(blob,
 				node, "samsung,efuse-max-value", -1);
-	error |= info->data.efuse_max_value;
+	error |= (info->data.efuse_max_value == -1);
 	info->data.slope = fdtdec_get_int(blob,
 				node, "samsung,slope", -1);
-	error |= info->data.slope;
+	error |= (info->data.slope == -1);
 	info->dc_value = fdtdec_get_int(blob,
 				node, "samsung,dc-value", -1);
-	error |= info->dc_value;
+	error |= (info->dc_value == -1);
 
-	if (error == -1) {
+	if (error) {
 		debug("fail to get tmu node properties\n");
 		return -1;
 	}
+#else
+	/* Non DT support may never be added. Just in case  */
+	return -1;
 #endif
 
 	return 0;
@@ -236,12 +264,12 @@ static int get_tmu_fdt_values(struct tmu_info *info, const void *blob)
  */
 static void tmu_setup_parameters(struct tmu_info *info)
 {
-	unsigned int te_code, con;
-	unsigned int warning_code, trip_code, hwtrip_code;
-	unsigned int cooling_temp;
-	unsigned int rising_value;
+	unsigned te_code, con;
+	unsigned warning_code, trip_code, hwtrip_code;
+	unsigned cooling_temp;
+	unsigned rising_value;
 	struct tmu_data *data = &info->data;
-	struct exynos5_tmu_reg *reg = (struct exynos5_tmu_reg *)info->tmu_base;
+	struct exynos5_tmu_reg *reg = info->tmu_base;
 
 	/* Must reload for reading efuse value from triminfo register */
 	writel(TRIMINFO_RELOAD, &reg->triminfo_control);
@@ -288,7 +316,7 @@ static void tmu_setup_parameters(struct tmu_info *info)
 
 	/* TMU core enable */
 	con = readl(&reg->tmu_control);
-	con |= THERM_TRIP_EN | CORE_EN;
+	con |= THERM_TRIP_EN | CORE_EN | (info->tmu_mux << 20);
 
 	writel(con, &reg->tmu_control);
 
@@ -314,6 +342,5 @@ int tmu_init(const void *blob)
 	tmu_setup_parameters(&gbl_info);
 	gbl_info.tmu_state = TMU_STATUS_NORMAL;
 ret:
-
 	return gbl_info.tmu_state;
 }
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 3c41242..e65125c 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -30,6 +30,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define RX_FIFO_COUNT_MASK	0xff
+#define RX_FIFO_FULL_MASK	(1 << 8)
+#define TX_FIFO_FULL_MASK	(1 << 24)
+
 static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
 {
 	u32 offset = dev_index * sizeof(struct s5p_uart);
@@ -87,8 +91,8 @@ int serial_init_dev(const int dev_index)
 {
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
-	/* reset and enable FIFOs, set triggers to the maximum */
-	writel(0, &uart->ufcon);
+	/* enable FIFOs */
+	writel(0x1, &uart->ufcon);
 	writel(0, &uart->umcon);
 	/* 8N1 */
 	writel(0x3, &uart->ulcon);
@@ -130,7 +134,8 @@ int serial_getc_dev(const int dev_index)
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
 	/* wait for character to arrive */
-	while (!(readl(&uart->utrstat) & 0x1)) {
+	while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
+					 RX_FIFO_FULL_MASK))) {
 		if (serial_err_check(dev_index, 0))
 			return 0;
 	}
@@ -146,7 +151,7 @@ void serial_putc_dev(const char c, const int dev_index)
 	struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
 
 	/* wait for room in the tx FIFO */
-	while (!(readl(&uart->utrstat) & 0x2)) {
+	while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
 		if (serial_err_check(dev_index, 1))
 			return;
 	}
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index ed0823b..c3606d5 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -319,10 +319,10 @@ void lcd_ctrl_init(void *lcdbase)
 #ifdef CONFIG_OF_CONTROL
 	if (exynos_fimd_parse_dt(gd->fdt_blob))
 		debug("Can't get proper panel info\n");
-#endif
+#else
 	/* initialize parameters which is specific to panel. */
 	init_panel_info(&panel_info);
-
+#endif
 	panel_width = panel_info.vl_width;
 	panel_height = panel_info.vl_height;
 
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 4b39844..3e32eee 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -90,9 +90,6 @@ extern void _start(void);
 extern ulong _rel_dyn_start_ofs;
 extern ulong _rel_dyn_end_ofs;
 
-/* Start/end of the relocation symbol table, as an offset from _start */
-extern ulong _dynsym_start_ofs;
-
 /* End of the region to be relocated, as an offset form _start */
 extern ulong _image_copy_end_ofs;
 
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index c15bbd8..a823f9f 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -34,6 +34,15 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #endif
 
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E500			/* BOOKE e500 family */
@@ -63,6 +72,7 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #endif
 
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
@@ -84,14 +94,15 @@
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_ENV_IS_NOWHERE
+#endif
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 
-#ifndef CONFIG_SYS_NO_FLASH
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -113,16 +124,18 @@
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
-#else /* CONFIG_SYS_NO_FLASH */
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
-#endif
 
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
@@ -223,7 +236,7 @@ unsigned long get_board_ddr_clk(void);
 /* NOR Flash Timing Params */
 #define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) | \
-				FTIM0_NOR_TEADC(0x01) | \
+				FTIM0_NOR_TEADC(0x04) | \
 				FTIM0_NOR_TEAHC(0x20))
 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
 				FTIM1_NOR_TRAD_NOR(0x1A) |\
@@ -600,6 +613,16 @@ unsigned long get_board_ddr_clk(void);
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index fd076e0..b5911c6 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -40,10 +40,34 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
 #endif
 
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
@@ -55,7 +79,11 @@
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on 9131 RDB */
+#if defined(CONFIG_SYS_CLK_100)
+#define CONFIG_SYS_CLK_FREQ    100000000 /* SYSCLK for 9131 RDB */
+#else
 #define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for 9131 RDB */
+#endif
 
 #define CONFIG_HWCONFIG
 /*
@@ -125,16 +153,21 @@ extern unsigned long get_sdram_size(void);
 
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses */
 							/* CONFIG_SYS_IMMR */
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 
 /*
  * Memory map
  *
  * 0x0000_0000	0x3FFF_FFFF	DDR			1G cacheable
  * 0x8800_0000	0x8810_0000	IFC internal SRAM		1M
+ * 0xB000_0000	0xB0FF_FFFF	DSP core M2 memory	16M
  * 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
  * 0xC1F0_0000	0xC1F3_FFFF	PA L2 SRAM Region 0	256K
  * 0xC1F8_0000	0xC1F9_FFFF	PA L2 SRAM Region 1	128K
  * 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
+ * 0xFF60_0000	0xFF6F_FFFF	DSP CCSR		1M
  * 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
  * 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND flash buffer	8M
  *
@@ -214,6 +247,9 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
 
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
 
@@ -295,7 +331,6 @@ extern unsigned long get_sdram_size(void);
 /*
  * Environment
  */
-#if defined(CONFIG_SYS_RAMBOOT)
 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS	0
@@ -305,15 +340,16 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_SIZE		0x2000
-#else
-#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE			0x2000
-#endif
-#else
-#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE		0x400
+#define CONFIG_ENV_SIZE		0x2000
 #endif
 
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
@@ -406,7 +442,9 @@ extern unsigned long get_sdram_size(void);
 	"fdtfile=bsc9131rdb.dtb\0"		\
 	"bdev=sda1\0"	\
 	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"	\
-	"othbootargs=ramdisk_size=600000 \0" \
+	"bootm_size=0x37000000\0"	\
+	"othbootargs=ramdisk_size=600000 " \
+	"default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
 	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
 	"console=$consoledev,$baudrate $othbootargs; "	\
 	"usb start;"			\
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 9d15d0e..3aa4443 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -49,6 +49,27 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
 #endif
 
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE		0x8ff80000
 #endif
@@ -57,11 +78,12 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0x8ffffffc
 #endif
 
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 
-
 /* High Level Configuration Options */
 #define CONFIG_BOOKE			/* BOOKE */
 #define CONFIG_E500			/* BOOKE e500 family */
@@ -222,6 +244,10 @@ combinations. this should be removed later
  * IFC Definitions
  */
 /* NOR Flash on IFC */
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
 #define CONFIG_SYS_FLASH_BASE		0x88000000
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* Max number of sector: 32M */
 
@@ -302,7 +328,9 @@ combinations. this should be removed later
 
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_FSL_QIXIS
+#endif
 #ifdef CONFIG_FSL_QIXIS
 #define CONFIG_SYS_FPGA_BASE	0xffb00000
 #define CONFIG_SYS_I2C_FPGA_ADDR	0x66
@@ -338,6 +366,22 @@ combinations. this should be removed later
 #endif
 
 /* Set up IFC registers for boot location NOR/NAND */
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
@@ -352,6 +396,7 @@ combinations. this should be removed later
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
 
 #define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
 #define CONFIG_BOARD_EARLY_INIT_R
@@ -374,6 +419,9 @@ combinations. this should be removed later
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
 
 #define CONFIG_SERIAL_MULTI	1 /* Enable both serial ports */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
@@ -503,7 +551,6 @@ combinations. this should be removed later
 /*
  * Environment
  */
-#if defined(CONFIG_SYS_RAMBOOT)
 #if defined(CONFIG_RAMBOOT_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
@@ -517,11 +564,15 @@ combinations. this should be removed later
 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_SIZE		0x2000
-#else
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE			0x2000
-#endif
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 5185597..7b28a27 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -31,10 +31,10 @@
 #define CONFIG_PHYS_64BIT
 #endif
 
-#ifdef CONFIG_P1010RDB
 #define CONFIG_P1010
+#define CONFIG_E500			/* BOOKE e500 family */
+#include <asm/config_mpc85xx.h>
 #define CONFIG_NAND_FSL_IFC
-#endif
 
 #ifdef CONFIG_SDCARD
 #define CONFIG_RAMBOOT_SDCARD
@@ -48,15 +48,25 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
 #endif
 
-#ifdef CONFIG_NAND	/* NAND Boot */
-#define CONFIG_RAMBOOT_NAND
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_TEXT_BASE_SPL	0xff800000
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE_SPL
-#else
-#define CONFIG_SYS_TEXT_BASE		0x11001000
-#endif /* CONFIG_NAND_SPL */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
 
 
@@ -74,8 +84,10 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 
 /* High Level Configuration Options */
@@ -242,7 +254,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW		CONFIG_SYS_CCSRBAR
 
 /* Don't relocate CCSRBAR while in NAND_SPL */
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 
@@ -268,6 +280,10 @@ extern unsigned long get_sdram_size(void);
  * IFC Definitions
  */
 /* NOR Flash on IFC */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 #define CONFIG_SYS_FLASH_BASE		0xee000000
 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
 
@@ -353,7 +369,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NAND_DDR_LAW		11
 
 /* Set up IFC registers for boot location NOR/NAND */
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SECBOOT)
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
@@ -385,15 +401,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
 #endif
 
-/* NAND boot: 8K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE	0x2000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START	0x11000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x10000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
 /* CPLD on IFC */
 #define CONFIG_SYS_CPLD_BASE		0xffb00000
 
@@ -421,14 +428,20 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_CS3_FTIM3		0x0
 #endif	/* CONFIG_SDCARD */
 
-#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
-    defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_SYS_RAMBOOT
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #else
 #undef CONFIG_SYS_RAMBOOT
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\
+	&& !defined(CONFIG_SECURE_BOOT)
+#define CONFIG_A003399_NOR_WORKAROUND
+#endif
+#endif
+
 #define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
 #define CONFIG_BOARD_EARLY_INIT_R
 
@@ -450,7 +463,7 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 
@@ -505,7 +518,7 @@ extern unsigned long get_sdram_size(void);
  * SPI interface will not be available in case of NAND boot SPI CS0 will be
  * used for SLIC
  */
-#if !defined(CONFIG_NAND_U_BOOT) || !defined(CONFIG_NAND_SECBOOT)
+#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
 /* eSPI - Enhanced SPI */
 #define CONFIG_FSL_ESPI
 #define CONFIG_SPI_FLASH
@@ -600,7 +613,6 @@ extern unsigned long get_sdram_size(void);
 /*
  * Environment
  */
-#if defined(CONFIG_SYS_RAMBOOT)
 #if defined(CONFIG_RAMBOOT_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_FSL_FIXED_MMC_LOCATION
@@ -615,16 +627,15 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
 #define CONFIG_ENV_SIZE		0x2000
-#elif defined(CONFIG_NAND_U_BOOT)
+#elif defined(CONFIG_NAND)
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET	CONFIG_SYS_NAND_U_BOOT_SIZE
+#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
-#else
+#elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE			0x2000
-#endif
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
new file mode 100644
index 0000000..fee8040
--- /dev/null
+++ b/include/configs/P1023RDB.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors:  Roy Zang <tie-fei.zang@freescale.com>
+ *	     Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		/* BOOKE */
+#define CONFIG_E500		/* BOOKE e500 family */
+#define CONFIG_MPC85xx
+#define CONFIG_P1023
+#define CONFIG_MP		/* support multiple processors */
+
+#define CONFIG_FSL_ELBC		/* Has Enhanced localbus controller */
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
+#define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3		/* PCIE controler 3 (slot 3) */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x02000000
+
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/* Implement conversion of addresses in the LBC */
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_DDR_SPD
+#define CONFIG_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SDRAM_SIZE		512u	/* DDR is 512M */
+#define CONFIG_SYS_SPD_BUS_NUM          0
+#define SPD_EEPROM_ADDRESS              0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x1fff_ffff	DDR			512M cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ * 0xff00_0000	0xff3f_ffff	DPAA_QBMAN		4M cacheable
+ * 0xff60_0000	0xff7f_ffff	CCSR			2M non-cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K cacheable TLB0
+ *
+ * Localbus non-cacheable
+ *
+ * 0xec00_0000	0xefff_ffff	NOR flash		64M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xec000000 /* start of FLASH 64M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				| BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f function */
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	  /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(6 * 1024 * 1024) /* Reserved for malloc */
+
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB		/* length 256K */ \
+				| OR_FCM_PGS \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX		1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+
+#define CONFIG_CMD_I2C
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME		"Slot 3"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000		/* Defind e1000 pci Ethernet card */
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR		0xfff80000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ	1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)   /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)   /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	(u-boot.bin) /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY -1	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* support Q/Bman */
+#define CONFIG_SYS_QMAN_MEM_BASE	0xff000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_BMAN_MEM_BASE	0xff200000
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+
+/* For FM */
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_ATHEROS
+#endif
+
+/* Default address of microcode for the Linux Fman driver */
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xeff40000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x2
+
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 9cd3a7c..4ea8717 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -77,6 +77,7 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
 
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index ce8f9b0..dd2b9c3 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -40,7 +40,7 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
-
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 
 #include "corenet_ds.h"
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 53979dd..48acee4 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -36,7 +36,7 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
-
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */
 
 #include "corenet_ds.h"
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index 778230d..d1e27c4 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -41,7 +41,7 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
-
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 
 #include "corenet_ds.h"
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index e9af825..8f29229 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -426,6 +426,7 @@
 #define CONFIG_SPL_BSS_MAX_SIZE		(64 << 10)
 
 #define CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_ENV_SUPPORT
 /* Place patched DT blob (fdt) at this address */
 #define CONFIG_SYS_SPL_ARGS_ADDR	0x01800000
 
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 737e19e..9c3c2cd 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -60,7 +60,7 @@
 	"rdaddr=0x81000000\0" \
 	"bootdir=/boot\0" \
 	"bootfile=uImage\0" \
-	"fdtfile=\0" \
+	"fdtfile=undefined\0" \
 	"console=ttyO0,115200n8\0" \
 	"optargs=\0" \
 	"mtdids=" MTDIDS_DEFAULT "\0" \
@@ -145,8 +145,9 @@
 		"if test $board_name = A33515BB; then " \
 			"setenv fdtfile am335x-evm.dtb; fi; " \
 		"if test $board_name = A335X_SK; then " \
-			"setenv fdtfile am335x-evmsk.dtb; fi\0" \
-
+			"setenv fdtfile am335x-evmsk.dtb; fi " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0"
 #endif
 
 #define CONFIG_BOOTCOMMAND \
@@ -355,6 +356,7 @@
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 #define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
 #define CONFIG_SPL_ETH_SUPPORT
 #define CONFIG_SPL_SPI_SUPPORT
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 0eea28c..c11f005 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -41,4 +41,7 @@
 #define CONFIG_BAUDRATE			115200
 
 #define CONFIG_SYS_OMAP_ABE_SYSCK
+
+#define CONSOLEDEV		"ttyO0"
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 41d6cf9..1632435 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -93,13 +93,15 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	EXYNOS_DEVICE_SETTINGS
 
-#define TZPC_BASE_OFFSET		0x10000
-
 /* SD/MMC configuration */
 #define CONFIG_GENERIC_MMC
 #define CONFIG_MMC
 #define CONFIG_SDHCI
 #define CONFIG_S5P_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
@@ -232,6 +234,10 @@
 #define SPI_FLASH_UBOOT_POS		(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
 
 #define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
 
 #define CONFIG_IRAM_STACK	0x02050000
 
@@ -262,6 +268,7 @@
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
 #define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_GIGADEVICE
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_SF_DEFAULT_SPEED		50000000
 #define EXYNOS5_SPI_NUM_CONTROLLERS	5
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
index 09b5798..e2b3b21 100644
--- a/include/configs/lacie_kw.h
+++ b/include/configs/lacie_kw.h
@@ -120,10 +120,14 @@
 #endif
 
 /*
+ * Enable platform initialisation via misc_init_r() function
+ */
+#define CONFIG_MISC_INIT_R
+
+/*
  * Ethernet Driver configuration
  */
 #ifdef CONFIG_CMD_NET
-#define CONFIG_MISC_INIT_R /* Call misc_init_r() to initialize MAC address */
 #define CONFIG_MVGBE_PORTS		{1, 0} /* enable port 0 only */
 #define CONFIG_NETCONSOLE
 #endif
@@ -153,6 +157,9 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4 /* 16-byte page size */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1 /* 8-bit device address */
+#if defined(CONFIG_NET2BIG_V2)
+#define CONFIG_SYS_I2C_G762_ADDR		0x3e
+#endif
 #endif /* CONFIG_CMD_I2C */
 
 /*
diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index 3e5d36b..2fa4382 100644
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -150,6 +150,7 @@
 	"console=ttyO2,115200n8\0" \
 	"fdt_high=0xffffffff\0" \
 	"fdtaddr=0x80f80000\0" \
+	"fdtfile=undefined\0" \
 	"bootpart=0:2\0" \
 	"bootdir=/boot\0" \
 	"bootfile=zImage\0" \
@@ -177,8 +178,12 @@
 			"setenv fdtfile omap4-sdp.dtb; fi; " \
 		"if test $board_name = panda; then " \
 			"setenv fdtfile omap4-panda.dtb; fi;" \
+		"if test $board_name = panda-a4; then " \
+			"setenv fdtfile omap4-panda-a4.dtb; fi;" \
 		"if test $board_name = panda-es; then " \
-			"setenv fdtfile omap4-panda-es.dtb; fi; \0" \
+			"setenv fdtfile omap4-panda-es.dtb; fi;" \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
 	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
 
 #define CONFIG_BOOTCOMMAND \
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index ddf2ad4..b87ee42 100644
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -136,9 +136,10 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
-	"console=ttyO2,115200n8\0" \
+	"console=" CONSOLEDEV ",115200n8\0" \
 	"fdt_high=0xffffffff\0" \
 	"fdtaddr=0x80f80000\0" \
+	"fdtfile=undefined\0" \
 	"bootpart=0:2\0" \
 	"bootdir=/boot\0" \
 	"bootfile=zImage\0" \
@@ -166,7 +167,11 @@
 		"bootz ${loadaddr} - ${fdtaddr}\0" \
 	"findfdt="\
 		"if test $board_name = omap5_uevm; then " \
-			"setenv fdtfile omap5-uevm.dtb; fi;\0 " \
+			"setenv fdtfile omap5-uevm.dtb; fi; " \
+		"if test $board_name = dra7xx; then " \
+			"setenv fdtfile dra7-evm.dtb; fi;" \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
 	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
 
 #define CONFIG_BOOTCOMMAND \
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index dea05bc..46dacc2 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -53,7 +53,9 @@
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 
-#define CONFIG_SYS_PROMPT		"OMAP5430 EVM # "
+#define CONFIG_SYS_PROMPT		"OMAP5432 uEVM # "
+
+#define CONSOLEDEV		"ttyO2"
 
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 #endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/origen.h b/include/configs/origen.h
index ff2b24d..e179911 100644
--- a/include/configs/origen.h
+++ b/include/configs/origen.h
@@ -96,6 +96,8 @@
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR	0x02020030
 
+#define CONFIG_SPL_TEXT_BASE	0x02021410
+
 #define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
 
 /* Miscellaneous configurable options */
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 2ecd105..9b16c47 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -231,6 +231,7 @@
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 #define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_NET_VCI_STRING	"pcm051 U-Boot SPL"
 #define CONFIG_SPL_ETH_SUPPORT
 #define CONFIG_SPL_SPI_SUPPORT
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
index b796b46..5e43066 100644
--- a/include/configs/smdkv310.h
+++ b/include/configs/smdkv310.h
@@ -95,6 +95,8 @@
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR	0x00002488
 
+#define CONFIG_SPL_TEXT_BASE	0x02021410
+
 #define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
 
 /* Miscellaneous configurable options */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index aa90249..92b2179 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -33,6 +33,15 @@
 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
 #endif
 
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 #define CONFIG_CMD_REGINFO
 
 /* High Level Configuration Options */
@@ -65,20 +74,22 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
 
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_ENV_IS_NOWHERE
+#endif
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 
-#ifndef CONFIG_SYS_NO_FLASH
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -100,18 +111,18 @@
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
-#else /* CONFIG_SYS_NO_FLASH */
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
-#endif
-
-
 
 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
@@ -633,6 +644,16 @@ unsigned long get_board_ddr_clk(void);
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
diff --git a/include/configs/trats.h b/include/configs/trats.h
index fd58558..c70838b 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -146,7 +146,8 @@
 
 #define CONFIG_DFU_ALT \
 	"u-boot mmc 80 400;" \
-	"uImage ext4 0 2\0" \
+	"uImage ext4 0 2;" \
+	"exynos4210-trats.dtb ext4 0 2\0"
 
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SYS_CONSOLE_INFO_QUIET
@@ -154,7 +155,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootk=" \
-		"run loaduimage; bootm 0x40007FC0\0" \
+		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
 	"updatemmc=" \
 		"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
 		"mmc boot 0 1 1 0\0" \
@@ -177,7 +178,7 @@
 	"mmcboot=" \
 		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
-		"run loaduimage; bootm 0x40007FC0\0" \
+		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
 	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
 	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
 	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
@@ -188,6 +189,8 @@
 	"nfsroot=/nfsroot/arm\0" \
 	"bootblock=" CONFIG_BOOTBLOCK "\0" \
 	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
+	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr}" \
+		"${fdtfile}\0" \
 	"mmcdev=0\0" \
 	"mmcbootpart=2\0" \
 	"mmcrootpart=5\0" \
@@ -212,7 +215,10 @@
 		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
 		   "setenv spl_imgsize;" \
 		   "setenv spl_imgaddr;" \
-		   "setenv spl_addr_tmp;\0"
+		   "setenv spl_addr_tmp;\0" \
+	"fdtaddr=40800000\0" \
+	"fdtfile=exynos4210-trats.dtb\0"
+
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
@@ -322,4 +328,7 @@
 #define CONFIG_USB_GADGET_MASS_STORAGE
 #endif
 
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT    1
+
 #endif	/* __CONFIG_H */
diff --git a/include/dwmmc.h b/include/dwmmc.h
index c8b1d40..e142f3e 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -123,6 +123,8 @@
 #define MSIZE(x)		((x) << 28)
 #define RX_WMARK(x)		((x) << 16)
 #define TX_WMARK(x)		(x)
+#define RX_WMARK_SHIFT		16
+#define RX_WMARK_MASK		(0xfff << RX_WMARK_SHIFT)
 
 #define DWMCI_IDMAC_OWN		(1 << 31)
 #define DWMCI_IDMAC_CH		(1 << 4)
@@ -144,6 +146,7 @@ struct dwmci_host {
 	unsigned int bus_hz;
 	int dev_index;
 	int buswidth;
+	u32 clksel_val;
 	u32 fifoth_val;
 	struct mmc *mmc;
 
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 1ece612..8845e29 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -89,6 +89,7 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS_TMU,	/* Exynos TMU */
 	COMPAT_SAMSUNG_EXYNOS_FIMD,	/* Exynos Display controller */
 	COMPAT_SAMSUNG_EXYNOS5_DP,	/* Exynos Display port controller */
+	COMPAT_SAMSUNG_EXYNOS5_DWMMC,	/* Exynos5 DWMMC controller */
 	COMPAT_MAXIM_MAX77686_PMIC,	/* MAX77686 PMIC */
 	COMPAT_GENERIC_SPI_FLASH,	/* Generic SPI Flash chip */
 	COMPAT_MAXIM_98095_CODEC,	/* MAX98095 Codec */
diff --git a/include/mmc.h b/include/mmc.h
index ea198d8..583c30e 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -93,6 +93,11 @@
 #define MMC_CMD_APP_CMD			55
 #define MMC_CMD_SPI_READ_OCR		58
 #define MMC_CMD_SPI_CRC_ON_OFF		59
+#define MMC_CMD_RES_MAN			62
+
+#define MMC_CMD62_ARG1			0xefac62ec
+#define MMC_CMD62_ARG2			0xcbaea7
+
 
 #define SD_CMD_SEND_RELATIVE_ADDR	3
 #define SD_CMD_SWITCH_FUNC		6
@@ -162,6 +167,7 @@
 #define EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
 #define EXT_CSD_RPMB_MULT		168	/* RO */
 #define EXT_CSD_ERASE_GROUP_DEF		175	/* R/W */
+#define EXT_CSD_BOOT_BUS_WIDTH		177
 #define EXT_CSD_PART_CONF		179	/* R/W */
 #define EXT_CSD_BUS_WIDTH		183	/* R/W */
 #define EXT_CSD_HS_TIMING		185	/* R/W */
@@ -187,6 +193,16 @@
 #define EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
 #define EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */
 
+#define EXT_CSD_BOOT_ACK_ENABLE			(1 << 6)
+#define EXT_CSD_BOOT_PARTITION_ENABLE		(1 << 3)
+#define EXT_CSD_PARTITION_ACCESS_ENABLE		(1 << 0)
+#define EXT_CSD_PARTITION_ACCESS_DISABLE	(0 << 0)
+
+#define EXT_CSD_BOOT_ACK(x)		(x << 6)
+#define EXT_CSD_BOOT_PART_NUM(x)	(x << 3)
+#define EXT_CSD_PARTITION_ACCESS(x)	(x << 0)
+
+
 #define R1_ILLEGAL_COMMAND		(1 << 22)
 #define R1_APP_CMD			(1 << 5)
 
@@ -214,6 +230,11 @@
 /* Maximum block size for MMC */
 #define MMC_MAX_BLOCK_LEN	512
 
+/* The number of MMC physical partitions.  These consist of:
+ * boot partitions (2), general purpose partitions (4) in MMC v4.4.
+ */
+#define MMC_NUM_BOOT_PARTITION	2
+
 struct mmc_cid {
 	unsigned long psn;
 	unsigned short oid;
@@ -298,6 +319,11 @@ int mmc_switch_part(int dev_num, unsigned int part_num);
 int mmc_getcd(struct mmc *mmc);
 int mmc_getwp(struct mmc *mmc);
 void spl_mmc_load(void) __noreturn;
+/* Function to change the size of boot partition and rpmb partitions */
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+					unsigned long rpmbsize);
+/* Function to send commands to open/close the specified boot partition */
+int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
 
 /**
  * Start device initialization and return immediately; it does not block on
diff --git a/lib/Makefile b/lib/Makefile
index 5d58609..a94830f 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)libgeneric.o
 
 ifndef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
 COBJS-$(CONFIG_AES) += aes.o
 COBJS-$(CONFIG_BZIP2) += bzlib.o
 COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o
@@ -36,13 +35,10 @@ COBJS-$(CONFIG_BZIP2) += bzlib_huffman.o
 COBJS-$(CONFIG_USB_TTY) += circbuf.o
 COBJS-y += crc7.o
 COBJS-y += crc16.o
-COBJS-y += display_options.o
-COBJS-y += errno.o
 COBJS-$(CONFIG_OF_CONTROL) += fdtdec.o
 COBJS-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
 COBJS-$(CONFIG_GZIP) += gunzip.o
 COBJS-$(CONFIG_GZIP_COMPRESSED) += gzip.o
-COBJS-y += hashtable.o
 COBJS-y += initcall.o
 COBJS-$(CONFIG_LMB) += lmb.o
 COBJS-y += ldiv.o
@@ -60,14 +56,12 @@ endif
 
 ifdef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += crc32.o
-ifneq ($(CONFIG_SPL_SPI_FLASH_SUPPORT)$(CONFIG_SPL_NET_SUPPORT),)
-COBJS-y += display_options.o
-endif
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += errno.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += hashtable.o
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
 endif
+COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
+COBJS-y += hashtable.o
+COBJS-y += errno.o
+COBJS-y += display_options.o
 COBJS-$(CONFIG_BCH) += bch.o
 COBJS-y += crc32.o
 COBJS-y += ctype.o
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 005ad3d..ad25a0c 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -62,6 +62,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
 	COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
 	COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
+	COMPAT(SAMSUNG_EXYNOS5_DWMMC, "samsung,exynos5250-dwmmc"),
 	COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
 	COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
 	COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile
deleted file mode 100644
index f7bdf92..0000000
--- a/nand_spl/board/freescale/p1010rdb/Makefile
+++ /dev/null
@@ -1,142 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2011 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-NAND_SPL := y
-CONFIG_SYS_TEXT_BASE_SPL := 0xff800000
-PAD_TO := 0xff802000
-
-include $(TOPDIR)/config.mk
-
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
-	   $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
-
-SOBJS	= start.o resetvec.o ticks.o
-COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
-	  nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
-
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(nandobj)board/$(BOARDDIR)
-
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all:	$(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot-nand_spl.lds
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)board/$(BOARDDIR) \
-		 -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)cache.c:
-	@rm -f $(obj)cache.c
-	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)cpu_init_early.c:
-	@rm -f $(obj)cpu_init_early.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
-
-$(obj)spl_minimal.c:
-	@rm -f $(obj)spl_minimal.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)fsl_law.c:
-	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
-
-$(obj)law.c:
-	@rm -f $(obj)law.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
-
-$(obj)nand_boot_fsl_ifc.c:
-	@rm -f $(obj)nand_boot_fsl_ifc.c
-	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \
-	       $(obj)nand_boot_fsl_ifc.c
-
-$(obj)ns16550.c:
-	@rm -f $(obj)ns16550.c
-	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
-
-$(obj)fixed_ivor.S:
-	@rm -f $(obj)fixed_ivor.S
-	ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
-
-$(obj)start.S: $(obj)fixed_ivor.S
-	@rm -f $(obj)start.S
-	ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
-
-$(obj)ticks.S:
-	@rm -f $(obj)ticks.S
-	ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
-
-$(obj)tlb.c:
-	@rm -f $(obj)tlb.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
-
-$(obj)tlb_table.c:
-	@rm -f $(obj)tlb_table.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-endif
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/spl/Makefile b/spl/Makefile
index d8fe948..01873de 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -98,6 +98,14 @@ LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
 LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
 endif
 
+ifneq ($(CONFIG_MX23)$(CONFIG_MX35),)
+LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+endif
+
+ifeq ($(SOC),exynos)
+LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
+endif
+
 # Add GCC lib
 ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
 PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
diff --git a/tools/pblimage.c b/tools/pblimage.c
index 508a747..5f39dc5 100644
--- a/tools/pblimage.c
+++ b/tools/pblimage.c
@@ -26,18 +26,14 @@
 #include "pblimage.h"
 
 /*
- * The PBL can load up to 64 bytes at a time, so we split the U-Boot
- * image into 64 byte chunks. PBL needs a command for each piece, of
- * the form "81xxxxxx", where "xxxxxx" is the offset. SYS_TEXT_BASE
- * is 0xFFF80000 for PBL boot, and PBL only cares about low 24-bit,
- * so it starts from 0x81F80000.
+ * Initialize to an invalid value.
  */
-static uint32_t next_pbl_cmd = 0x81F80000;
+static uint32_t next_pbl_cmd = 0x82000000;
 /*
  * need to store all bytes in memory for calculating crc32, then write the
  * bytes to image file for PBL boot.
  */
-static unsigned char mem_buf[600000];
+static unsigned char mem_buf[1000000];
 static unsigned char *pmem_buf = mem_buf;
 static int pbl_size;
 static char *fname = "Unknown";
@@ -52,6 +48,27 @@ static union
 
 #define ENDIANNESS ((char)endian_test.l)
 
+/*
+ * The PBL can load up to 64 bytes at a time, so we split the U-Boot
+ * image into 64 byte chunks. PBL needs a command for each piece, of
+ * the form "81xxxxxx", where "xxxxxx" is the offset. Calculate the
+ * start offset by subtracting the size of the u-boot image from the
+ * top of the allowable 24-bit range.
+ */
+static void init_next_pbl_cmd(FILE *fp_uboot)
+{
+	struct stat st;
+	int fd = fileno(fp_uboot);
+
+	if (fstat(fd, &st) == -1) {
+		printf("Error: Could not determine u-boot image size. %s\n",
+			strerror(errno));
+		exit(EXIT_FAILURE);
+	}
+
+	next_pbl_cmd = 0x82000000 - st.st_size;
+}
+
 static void generate_pbl_cmd(void)
 {
 	uint32_t val = next_pbl_cmd;
@@ -80,6 +97,7 @@ static void pbl_fget(size_t size, FILE *stream)
 /* load split u-boot with PBI command 81xxxxxx. */
 static void load_uboot(FILE *fp_uboot)
 {
+	init_next_pbl_cmd(fp_uboot);
 	while (next_pbl_cmd < 0x82000000) {
 		generate_pbl_cmd();
 		pbl_fget(64, fp_uboot);