From: Dave Stevenson Date: Thu, 13 Jan 2022 11:30:42 +0000 (+0000) Subject: drm/vc4: Disable Gamma control on HVS5 due to issues writing the table X-Git-Tag: accepted/tizen/unified/20240422.153132~963 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f9beee5e26a173eed41bde93514c0e9393caaf7f;p=platform%2Fkernel%2Flinux-rpi.git drm/vc4: Disable Gamma control on HVS5 due to issues writing the table Still under investigation, but the conditions under which the HVS will accept values written to the gamma PWL are not straightforward. Disable gamma on HVS5 again until it can be resolved to avoid gamma being enabled with an incorrect table. Signed-off-by: Dave Stevenson --- diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 250f3f6..8f5ac28 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -1357,15 +1357,9 @@ int __vc4_crtc_init(struct drm_device *drm, if (!vc4->is_vc5) { drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); - } else { - /* This is a lie for hvs5 which uses a 16 point PWL, but it - * allows for something smarter than just 16 linearly spaced - * segments. Conversion is done in vc5_hvs_update_gamma_lut. - */ - drm_mode_crtc_set_gamma_size(crtc, 256); + drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); } - drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); if (!vc4->is_vc5) { /* We support CTM, but only for one CRTC at a time. It's therefore