From: Feifei Xu Date: Fri, 26 Jan 2018 07:10:55 +0000 (+0800) Subject: drm/amdgpu/soc15: Set common clockgating for vega20. X-Git-Tag: v4.19~774^2~6^2~99 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f980d127dba80214b4d793942492d3a4e6c46be0;p=platform%2Fkernel%2Flinux-rpi.git drm/amdgpu/soc15: Set common clockgating for vega20. Same as vega10 for now. Reviewed-by: Christian König Signed-off-by: Feifei Xu Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index f45bea8..1fd75f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -875,6 +875,7 @@ static int soc15_common_set_clockgating_state(void *handle, switch (adev->asic_type) { case CHIP_VEGA10: case CHIP_VEGA12: + case CHIP_VEGA20: adev->nbio_funcs->update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE ? true : false); adev->nbio_funcs->update_medium_grain_light_sleep(adev,