From: Nanley Chery Date: Fri, 9 Oct 2020 17:07:51 +0000 (-0700) Subject: iris: Add fast-clear restriction for 8bpp surfaces X-Git-Tag: upstream/21.0.0~3710 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f94ba6b6f56afdc443e22b1cafcd9d3f6f3f007e;p=platform%2Fupstream%2Fmesa.git iris: Add fast-clear restriction for 8bpp surfaces For 8bpp surfaces on TGL, prevent LOD1+ from being fast-cleared. This will be relevant once ISL starts allowing CCS for 8bpp surfaces with more than 2 miplevels. I verified the problem behind this restriction with a modified version of the fbo-clearmipmap piglit test. Reviewed-by: Sagar Ghuge Part-of: --- diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c index 43af59c..a4d45a4 100644 --- a/src/gallium/drivers/iris/iris_clear.c +++ b/src/gallium/drivers/iris/iris_clear.c @@ -114,6 +114,23 @@ can_fast_clear_color(struct iris_context *ice, if (!iris_is_color_fast_clear_compatible(ice, res->surf.format, color)) return false; + /* The RENDER_SURFACE_STATE page for TGL says: + * + * For an 8 bpp surface with NUM_MULTISAMPLES = 1, Surface Width not + * multiple of 64 pixels and more than 1 mip level in the view, Fast Clear + * is not supported when AUX_CCS_E is set in this field. + * + * The granularity of a fast-clear is one CCS element. For an 8 bpp primary + * surface, this maps to 32px x 4rows. Due to the surface layout parameters, + * if LOD0's width isn't a multiple of 64px, LOD1 and LOD2+ will share CCS + * elements. Assuming LOD2 exists, don't fast-clear any level above LOD0 + * to avoid stomping on other LODs. + */ + if (level > 0 && util_format_get_blocksizebits(p_res->format) == 8 && + res->aux.usage == ISL_AUX_USAGE_GEN12_CCS_E && p_res->width0 % 64) { + return false; + } + return true; }