From: Thomas Richter Date: Mon, 13 Mar 2023 08:01:57 +0000 (+0100) Subject: perf vendor events s390: Add cache metrics for z16 X-Git-Tag: v6.6.7~2868^2~294 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f8a6cea4839bc8c76804b301dbb5522a6cacf6d5;p=platform%2Fkernel%2Flinux-starfive.git perf vendor events s390: Add cache metrics for z16 Add metrics for s390 z16 - Percentage sourced from Level 2 cache - Percentage sourced from Level 3 on same chip cache - Percentage sourced from Level 4 Local cache on same book - Percentage sourced from Level 4 Remote cache on different book - Percentage sourced from memory For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M l4rp -- dd if=/dev/zero of=/dev/null bs=10M count=10K .... dd output deleted Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=10M count=10K': 0 IDCW_OFF_DRAWER_CHIP_HIT # 0.00 l4rp 431,866 L1I_DIR_WRITES 2,395 IDCW_OFF_DRAWER_IV 0 ICW_OFF_DRAWER 0 IDCW_OFF_DRAWER_DRAWER_HIT 1,437 DCW_OFF_DRAWER 425,960,793 L1D_DIR_WRITES 12.165030699 seconds time elapsed 0.001037000 seconds user 12.162140000 seconds sys # Signed-off-by: Thomas Richter Acked-by: Ian Rogers Acked-By: Sumanth Korikkar Cc: Heiko Carstens Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230313080201.2440201-1-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json index 86bf83b..dde0735 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json @@ -18,5 +18,30 @@ "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 2 cache", + "MetricName": "l2p", + "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 3 on same chip cache", + "MetricName": "l3p", + "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", + "MetricName": "l4lp", + "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", + "MetricName": "l4rp", + "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from memory", + "MetricName": "memp", + "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" } ]