From: Paul Burton <paul.burton@imgtec.com>
Date: Wed, 21 Sep 2016 10:18:51 +0000 (+0100)
Subject: MIPS: If we don't need DDR for cache init, init cache first
X-Git-Tag: v2016.11-rc1~120^2~22
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f8981277f581564bf701d310fe0f68903cf3f542;p=platform%2Fkernel%2Fu-boot.git

MIPS: If we don't need DDR for cache init, init cache first

On systems where cache initialisation doesn't require zeroed memory (ie.
systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)
perform cache initialisation prior to lowlevel_init & DDR
initialisation. This allows for DDR initialisation code to run cached &
thus significantly faster.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 6aec430..6f1d219 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -142,15 +142,24 @@ reset:
 	PTR_L	gp, 0(ra)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
+# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
 	/* Initialize any external memory */
 	PTR_LA	t9, lowlevel_init
 	jalr	t9
 	 nop
+# endif
 
 	/* Initialize caches... */
 	PTR_LA	t9, mips_cache_reset
 	jalr	t9
 	 nop
+
+# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
+	/* Initialize any external memory */
+	PTR_LA	t9, lowlevel_init
+	jalr	t9
+	 nop
+# endif
 #endif
 
 	/* Set up temporary stack */