From: Marcin Ślusarz <marcin.slusarz@intel.com>
Date: Tue, 21 Jun 2022 08:47:10 +0000 (+0200)
Subject: intel/compiler: assert that base is 0 for [load|store]_shared intrins
X-Git-Tag: upstream/22.3.5~7054
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f871aa10a117168ed375bbe9e25ca3496fbb1569;p=platform%2Fupstream%2Fmesa.git

intel/compiler: assert that base is 0 for [load|store]_shared intrins

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17143>
---

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 9864acb..4117de8 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3895,6 +3895,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
 
    case nir_intrinsic_load_shared: {
       assert(devinfo->ver >= 7);
+      assert(nir_intrinsic_base(instr) == 0);
 
       const unsigned bit_size = nir_dest_bit_size(instr->dest);
       fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
@@ -3931,6 +3932,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
 
    case nir_intrinsic_store_shared: {
       assert(devinfo->ver >= 7);
+      assert(nir_intrinsic_base(instr) == 0);
 
       const unsigned bit_size = nir_src_bit_size(instr->src[0]);
       fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];