From: Nicholas Piggin <npiggin@gmail.com>
Date: Thu, 20 Oct 2016 06:59:10 +0000 (+1100)
Subject: ppc: fix MSR_ME handling for system reset interrupt
X-Git-Tag: TizenStudio_2.0_p2.3.2~9^2~14^2~5^2~101^2~54
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f85bcec31ee578eccf6182be158d6ac6d9b90a4c;p=sdk%2Femulator%2Fqemu.git

ppc: fix MSR_ME handling for system reset interrupt

Power ISA specifies ME bit handling for system reset interrupt:

    if the interrupt occurred while the thread was in power-saving
    mode, set to 1; otherwise not altered

Power ISA 3.0, section 6.5 "Interrupt Definitions", Figure 64.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---

diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 921c39d..53c4075 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -385,11 +385,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
         srr1 = SPR_BOOKE_CSRR1;
         break;
     case POWERPC_EXCP_RESET:     /* System reset exception                   */
+        /* A power-saving exception sets ME, otherwise it is unchanged */
         if (msr_pow) {
             /* indicate that we resumed from power save mode */
             msr |= 0x10000;
-        } else {
-            new_msr &= ~((target_ulong)1 << MSR_ME);
+            new_msr |= ((target_ulong)1 << MSR_ME);
         }
 
         new_msr |= (target_ulong)MSR_HVB;