From: Geert Uytterhoeven Date: Wed, 21 Nov 2018 09:42:24 +0000 (+0100) Subject: clk: renesas: r8a774a1: Add CPEX clock X-Git-Tag: v5.4-rc1~1882^2~7^2^2~13 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f845b01d478a4d139fe3493f1e6ec8d9110ce56c;p=platform%2Fkernel%2Flinux-rpi.git clk: renesas: r8a774a1: Add CPEX clock Implement support for the CPEX clock on RZ/G2M. This clock can be selected as a clock source for CMT1 (Compare Match Timer Type 1). Signed-off-by: Geert Uytterhoeven Acked-by: Stephen Boyd --- diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index b0da342..10e8525 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -100,6 +100,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A774A1_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),