From: Brian Paul Date: Tue, 11 Jul 2017 20:56:00 +0000 (-0600) Subject: svga: fix texture swizzle writemasking X-Git-Tag: upstream/18.1.0~7955 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f7e78abdf45b26f3991dc336120162ae01b208f1;p=platform%2Fupstream%2Fmesa.git svga: fix texture swizzle writemasking Commit bfe1e7737a76e3b046 changed how texture swizzles are set up. This exposed a latent bug in the VMware driver: we were ignoring the texture instruction's writemask when applying the 0 and 1 swizzle terms. This wasn't caught by the Piglit texture swizzle test because it only exercises fixed function (no write masking). Fixes issues seen with ETQW apitrace. CC: Reviewed-by: Charmaine Lee --- diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c index d29ac28..96269cb 100644 --- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c +++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c @@ -5047,6 +5047,7 @@ end_tex_swizzle(struct svga_shader_emitter_v10 *emit, ((swz_g == PIPE_SWIZZLE_0) << 1) | ((swz_b == PIPE_SWIZZLE_0) << 2) | ((swz_a == PIPE_SWIZZLE_0) << 3)); + writemask_0 &= swz->inst_dst->Register.WriteMask; if (writemask_0) { struct tgsi_full_src_register zero = int_tex ? @@ -5065,6 +5066,7 @@ end_tex_swizzle(struct svga_shader_emitter_v10 *emit, ((swz_g == PIPE_SWIZZLE_1) << 1) | ((swz_b == PIPE_SWIZZLE_1) << 2) | ((swz_a == PIPE_SWIZZLE_1) << 3)); + writemask_1 &= swz->inst_dst->Register.WriteMask; if (writemask_1) { struct tgsi_full_src_register one = int_tex ?