From: Kenneth Graunke <kenneth@whitecape.org>
Date: Mon, 3 Nov 2014 23:34:56 +0000 (-0800)
Subject: i965: Disable fast color clears on Skylake for now.
X-Git-Tag: upstream/17.1.0~22603
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f7819650979d1fa5339af3eacfa1af1090bf53e8;p=platform%2Fupstream%2Fmesa.git

i965: Disable fast color clears on Skylake for now.

We're not programming the clear values yet, so this won't work.

This patch should be (effectively) reverted eventually.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
---

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 0e5fef5..1231420 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -242,7 +242,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
    }
 
    /* Clear color buffers with fast clear or at least rep16 writes. */
-   if (brw->gen >= 6 && mask & BUFFER_BITS_COLOR) {
+   if (brw->gen >= 6 && brw->gen < 9 && (mask & BUFFER_BITS_COLOR)) {
       if (brw_meta_fast_clear(brw, fb, mask, partial_clear)) {
          debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
          mask &= ~BUFFER_BITS_COLOR;