From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Sat, 5 Nov 2022 18:20:41 +0000 (-0700)
Subject: AMDGPU: Fix missing divergence tests for csub intrinsics
X-Git-Tag: upstream/17.0.6~28378
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f72416e974b3d831ffa2672202a782b17b4cd5b4;p=platform%2Fupstream%2Fllvm.git

AMDGPU: Fix missing divergence tests for csub intrinsics
---

diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll
index 0833c35..dec529a2 100644
--- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll
+++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll
@@ -41,5 +41,14 @@ declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64,
 declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #1
 declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #1
 
+; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %val)
+define amdgpu_kernel void @test_atomic_csub_i32(i32 addrspace(1)* %ptr, i32 %val) #0 {
+  %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %val)
+  store i32 %ret, i32 addrspace(1)* %ptr, align 4
+  ret void
+}
+
+declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #1
+
 attributes #0 = { nounwind }
-attributes #1 = { nounwind argmemonly }
+attributes #1 = { argmemonly nounwind willreturn }
diff --git a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/atomics.ll b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/atomics.ll
index dfb54c8..932ac8e 100644
--- a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/atomics.ll
+++ b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/atomics.ll
@@ -41,5 +41,14 @@ declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64,
 declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #1
 declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #1
 
+; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %val)
+define amdgpu_kernel void @test_atomic_csub_i32(i32 addrspace(1)* %ptr, i32 %val) #0 {
+  %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %val)
+  store i32 %ret, i32 addrspace(1)* %ptr, align 4
+  ret void
+}
+
+declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #1
+
 attributes #0 = { nounwind }
-attributes #1 = { nounwind argmemonly }
+attributes #1 = { argmemonly nounwind willreturn }