From: Geert Uytterhoeven Date: Wed, 21 Nov 2018 09:44:16 +0000 (+0100) Subject: clk: renesas: r8a77965: Add CPEX clock X-Git-Tag: v5.4-rc1~1882^2~7^2^2~10 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f70f4be7339dfca0ef684046c1583cce61b039fc;p=platform%2Fkernel%2Flinux-rpi.git clk: renesas: r8a77965: Add CPEX clock Implement support for the CPEX clock on R-Car M3-N. This clock can be selected as a clock source for CMT1 (Compare Match Timer Type 1). Signed-off-by: Geert Uytterhoeven Acked-by: Stephen Boyd --- diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 1fcc411..eb1cca5 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -100,6 +100,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),