From: Wang, Pengfei <pengfei.wang@intel.com>
Date: Wed, 28 Apr 2021 07:56:17 +0000 (+0800)
Subject: [X86][AMX][NFC] Add more comments and remove unnecessary check found by Clocwork
X-Git-Tag: llvmorg-14-init~8232
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f69adfb87f9924c6a1920cff95ace3df17623356;p=platform%2Fupstream%2Fllvm.git

[X86][AMX][NFC] Add more comments and remove unnecessary check found by Clocwork
---

diff --git a/llvm/lib/Target/X86/X86PreTileConfig.cpp b/llvm/lib/Target/X86/X86PreTileConfig.cpp
index 9164dfd..2b3a7ac 100644
--- a/llvm/lib/Target/X86/X86PreTileConfig.cpp
+++ b/llvm/lib/Target/X86/X86PreTileConfig.cpp
@@ -71,9 +71,13 @@ struct MIRef {
   }
   bool operator!=(const MIRef &RHS) const { return !(*this == RHS); }
   bool operator<(const MIRef &RHS) const {
+    // Comparison between different BBs happens when inserting a MIRef into set.
+    // So we compare MBB first to make the insertion happy.
     return MBB < RHS.MBB || (MBB == RHS.MBB && Pos < RHS.Pos);
   }
   bool operator>(const MIRef &RHS) const {
+    // Comparison between different BBs happens when inserting a MIRef into set.
+    // So we compare MBB first to make the insertion happy.
     return MBB > RHS.MBB || (MBB == RHS.MBB && Pos > RHS.Pos);
   }
 };
@@ -205,8 +209,9 @@ void X86PreTileConfig::collectShapeInfo(MachineInstr &MI) {
   while (!WorkList.empty()) {
     Register R = WorkList.pop_back_val();
     MachineInstr *DefMI = MRI->getVRegDef(R);
+    assert(DefMI && "R must has one define instruction");
     MachineBasicBlock *DefMBB = DefMI->getParent();
-    if (!DefMI || DefMI->isMoveImmediate() || !DefVisited.insert(DefMI).second)
+    if (DefMI->isMoveImmediate() || !DefVisited.insert(DefMI).second)
       continue;
     if (DefMI->isPHI()) {
       for (unsigned I = 1; I < DefMI->getNumOperands(); I += 2)