From: YunQiang Su <wzssyqa@gmail.com>
Date: Fri, 16 Mar 2018 06:58:22 +0000 (+0300)
Subject: Support MIPS rel6
X-Git-Tag: v7.6.4~3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f69abe165db7181728cdb0ddc670541b9d434db7;p=platform%2Fupstream%2Flibatomic_ops.git

Support MIPS rel6

Don't set mips2/3 for mips r6.  MIPS release 6 changes the encoding of
some instructions, including ll/sc.  Setting mips2/3 here produces the
binary with the old encoding (not compatible with mips r6).

This patch has no effect if gcc 4.9+ or clang 3.5+ unless
AO_DISABLE_GCC_ATOMICS is defined manually in CFLAGS.

* src/atomic_ops/sysdeps/gcc/mips.h [AO_DISABLE_GCC_ATOMICS
&& __mips_isa_rev>=6] (AO_MIPS_SET_ISA): Define to empty string
(instead of ".set mips2" or ".set mips3").
---

diff --git a/src/atomic_ops/sysdeps/gcc/mips.h b/src/atomic_ops/sysdeps/gcc/mips.h
index d7a3620..34cc4fb 100644
--- a/src/atomic_ops/sysdeps/gcc/mips.h
+++ b/src/atomic_ops/sysdeps/gcc/mips.h
@@ -41,14 +41,23 @@
 
 # if !defined(_ABI64) || _MIPS_SIM != _ABI64
 #   define AO_T_IS_INT
-#   define AO_MIPS_SET_ISA    "       .set mips2\n"
+#   if __mips_isa_rev >= 6
+      /* Encoding of ll/sc in mips rel6 differs from that of mips2/3. */
+#     define AO_MIPS_SET_ISA  ""
+#   else
+#     define AO_MIPS_SET_ISA  "       .set mips2\n"
+#   endif
 #   define AO_MIPS_LL_1(args) "       ll " args "\n"
 #   define AO_MIPS_SC(args)   "       sc " args "\n"
 # else
-#   define AO_MIPS_SET_ISA    "       .set mips3\n"
+#   if __mips_isa_rev >= 6
+#     define AO_MIPS_SET_ISA  ""
+#   else
+#     define AO_MIPS_SET_ISA  "       .set mips3\n"
+#   endif
 #   define AO_MIPS_LL_1(args) "       lld " args "\n"
 #   define AO_MIPS_SC(args)   "       scd " args "\n"
-# endif
+# endif /* _MIPS_SIM == _ABI64 */
 
 #ifdef AO_ICE9A1_LLSC_WAR
   /* ICE9 rev A1 chip (used in very few systems) is reported to */