From: Palmer Dabbelt Date: Sat, 12 Jun 2021 03:40:42 +0000 (-0700) Subject: RISC-V: Use asm-generic for {in,out}{bwlq} X-Git-Tag: v5.15~756^2~9 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f627476e8f1a15495fb363e4a25f495460e8c969;p=platform%2Fkernel%2Flinux-starfive.git RISC-V: Use asm-generic for {in,out}{bwlq} The asm-generic implementation is functionally identical to the RISC-V version. Signed-off-by: Palmer Dabbelt Reviewed-by: Anup Patel Signed-off-by: Palmer Dabbelt --- diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index c025a74..69605a4 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -52,19 +52,6 @@ #define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); #define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); -#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) -#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) -#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) - -#define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) -#define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) -#define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) - -#ifdef CONFIG_64BIT -#define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; }) -#define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); }) -#endif - /* * Accesses from a single hart to a single I/O address must be ordered. This * allows us to use the raw read macros, but we still need to fence before and