From: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Date: Tue, 28 Oct 2014 05:52:19 +0000 (+0530)
Subject: ARM: zynq: slcr: Dont modify the reserved bits
X-Git-Tag: v2015.04-rc1~39^2~10
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f60c6fbbc658201f968a22addff7dd1acbe5eaca;p=platform%2Fkernel%2Fu-boot.git

ARM: zynq: slcr: Dont modify the reserved bits

Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 934ccc3..2521589 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void)
 	zynq_slcr_unlock();
 
 	/* Disable AXI interface by asserting FPGA resets */
-	writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
+	writel(0xF, &slcr_base->fpga_rst_ctrl);
 
 	/* Set Level Shifters DT618760 */
 	writel(0xA, &slcr_base->lvl_shftr_en);