From: edward shu <edward.shu@sun.com>
Date: Wed, 15 Apr 2009 00:19:09 +0000 (-0700)
Subject: Sun bug 6785726: libpciaccess needs to use the correct BAR index on solaris
X-Git-Tag: libpciaccess-0.10.6~8
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f6084593c275c5dc1d6154f292991b20bffd68c2;p=platform%2Fupstream%2Flibpciaccess.git

Sun bug 6785726: libpciaccess needs to use the correct BAR index on solaris

<http://bugs.opensolaris.org/bugdatabase/view_bug.do?bug_id=6785726>

Signed-off-by: Alan Coopersmith <alan.coopersmith@sun.com>
---

diff --git a/src/solx_devfs.c b/src/solx_devfs.c
index 99ee1ac..97de339 100644
--- a/src/solx_devfs.c
+++ b/src/solx_devfs.c
@@ -734,6 +734,7 @@ pci_device_solx_devfs_probe( struct pci_device * dev )
     int i;
     pciaddr_t bytes;
     int len = 0;
+    uint ent = 0;
 
     err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes );
     args.node = DI_NODE_NIL;
@@ -815,13 +816,21 @@ pci_device_solx_devfs_probe( struct pci_device * dev )
     }
 
     /*
-     * solaris has its own BAR index. To be sure that
-     * Xorg has the same BAR number as solaris. ????
+     * Solaris has its own BAR index.
+     * Linux give two region slot for 64 bit address.
      */
     for (i = 0; i < len; i = i + CELL_NUMS_1275) {
-	int ent = i/CELL_NUMS_1275;
 
 	reg = (pci_regspec_t *)&regbuf[i];
+	ent = reg->pci_phys_hi & 0xff;
+	/*
+	 * G35 broken in BAR0
+	 */
+	ent = (ent - PCI_CONF_BASE0) >> 2;
+	if (ent >= 6) {
+	    fprintf(stderr, "error ent = %d\n", ent);
+	    break;
+	}
 
 	/*
 	 * non relocatable resource is excluded
@@ -835,6 +844,16 @@ pci_device_solx_devfs_probe( struct pci_device * dev )
 	    dev->regions[ent].is_prefetchable = 1;
 	}
 
+
+	/*
+	 * We split the shift count 32 into two 16 to
+	 * avoid the complaining of the compiler
+	 */
+	dev->regions[ent].base_addr = reg->pci_phys_low +
+	    ((reg->pci_phys_mid << 16) << 16);
+	dev->regions[ent].size = reg->pci_size_low +
+	    ((reg->pci_size_hi << 16) << 16);
+
 	switch (reg->pci_phys_hi & PCI_REG_ADDR_M) {
 	    case PCI_ADDR_IO:
 		dev->regions[ent].is_IO = 1;
@@ -843,17 +862,11 @@ pci_device_solx_devfs_probe( struct pci_device * dev )
 		break;
 	    case PCI_ADDR_MEM64:
 		dev->regions[ent].is_64 = 1;
+		/*
+		 * Skip one slot for 64 bit address
+		 */
 		break;
 	}
-
-	/*
-	 * We split the shift count 32 into two 16 to
-	 * avoid the complaining of the compiler
-	 */
-	dev->regions[ent].base_addr = reg->pci_phys_low +
-	    ((reg->pci_phys_mid << 16) << 16);
-	dev->regions[ent].size = reg->pci_size_low +
-	    ((reg->pci_size_hi << 16) << 16);
     }
 
     return (err);