From: Benjamin Kramer <benny.kra@googlemail.com>
Date: Sun, 16 Apr 2017 20:13:08 +0000 (+0000)
Subject: [X86] Remove special handling for 16 bit for A asm constraints.
X-Git-Tag: llvmorg-5.0.0-rc1~7580
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f5f593b674ed031f3f5aa2c44ac705547532d5cb;p=platform%2Fupstream%2Fllvm.git

[X86] Remove special handling for 16 bit for A asm constraints.

Our 16 bit support is assembler-only + the terrible hack that is
.code16gcc. Simply using 32 bit registers does the right thing for the
latter.

Fixes PR32681.

llvm-svn: 300429
---

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7ff4830..6bf3672 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35922,14 +35922,11 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       if (Subtarget.is64Bit()) {
         Res.first = X86::RAX;
         Res.second = &X86::GR64_ADRegClass;
-      } else if (Subtarget.is32Bit()) {
+      } else {
+        assert((Subtarget.is32Bit() || Subtarget.is16Bit()) &&
+               "Expecting 64, 32 or 16 bit subtarget");
         Res.first = X86::EAX;
         Res.second = &X86::GR32_ADRegClass;
-      } else if (Subtarget.is16Bit()) {
-        Res.first = X86::AX;
-        Res.second = &X86::GR16_ADRegClass;
-      } else {
-        llvm_unreachable("Expecting 64, 32 or 16 bit subtarget");
       }
       return Res;
     }
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index c177ba1..d235d2b 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -438,7 +438,6 @@ def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
                                           (add LOW32_ADDR_ACCESS, RBP)>;
 
 // A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
-def GR16_AD : RegisterClass<"X86", [i16], 16, (add AX, DX)>;
 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
 def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
 
diff --git a/llvm/test/CodeGen/X86/x86-16.ll b/llvm/test/CodeGen/X86/x86-16.ll
index 775b2c4..55b53a8 100644
--- a/llvm/test/CodeGen/X86/x86-16.ll
+++ b/llvm/test/CodeGen/X86/x86-16.ll
@@ -12,9 +12,16 @@ define i32 @main() #0 {
 ; CHECK: .code16
 ; CHECK-LABEL: main
 
+define i64 @foo(i32 %index) #0 {
+  %asm = tail call i64 asm "rdmsr", "=A,{cx},~{dirflag},~{fpsr},~{flags}"(i32 %index)
+  ret i64 %asm
+}
+
+; CHECK-LABEL: foo
+; CHECK: rdmsr
 
 attributes #0 = { nounwind }
 
 !llvm.ident = !{!0}
 
-!0 = !{!"clang version 3.9.0 (trunk 265439) (llvm/trunk 265567)"}
\ No newline at end of file
+!0 = !{!"clang version 3.9.0 (trunk 265439) (llvm/trunk 265567)"}