From: Matthew Green Date: Wed, 17 Oct 2001 13:13:16 +0000 (+0000) Subject: [gas/ChangeLog] X-Git-Tag: cygnus_cvs_20020108_pre~1012 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f5c120c5dcc817baeafc0db53d03e84735616eb2;p=platform%2Fupstream%2Fbinutils.git [gas/ChangeLog] * config/tc-ppc.c (md_show_usage): Add missing -maltivec, -m7400, -m7410, -m7450 and -m7455 options. [gas/testsuite/ChangeLog] * gas/ppc/altivec.s: New test for AltiVec. * gas/ppc/altivec.d: New file. * gas/ppc/ppc.exp: Test altivec.s [include/opcode/ChangeLog] * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. [opcodes/ChangeLog] * ppc-opc.c (STRM): New AltiVec operand. (XDSS): New AltiVec instruction form. (mtvscr): Correct operand list. (dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index b3551fb..435d388 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2001-10-17 matthew green + + * config/tc-ppc.c (md_show_usage): Add missing -maltivec, -m7400, + -m7410, -m7450 and -m7455 options. + 2001-10-17 Alan Modra * config/tc-ppc.c (PPC_HA, PPC_HIGHERA, PPC_HIGHESTA): Simplify. diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 79a8526..d0e8db8 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1028,10 +1028,13 @@ PowerPC options:\n\ -mppc, -mppc32, -m603, -m604\n\ generate code for Motorola PowerPC 603/604\n\ -m403, -m405 generate code for Motorola PowerPC 403/405\n\ +-m7400, -m7410, -m7450, -m7455\n\ + generate code For Motorola PowerPC 7400/7410/7450/7455\n\ -mppc64, -m620 generate code for Motorola PowerPC 620\n\ -mppc64bridge generate code for PowerPC 64, including bridge insns\n\ --mbooke64 generate code for 64-bit Motorola BookE\n\ --mbooke, mbooke32 generate code for 32-bit Motorola BookE\n\ +-mbooke64 generate code for 64-bit Motorola BookE\n\ +-mbooke, mbooke32 generate code for 32-bit Motorola BookE\n\ +-maltivec generate code for AltiVec\n\ -mcom generate code Power/PowerPC common instructions\n\ -many generate code for any architecture (PWR/PWRX/PPC)\n\ -mregnames Allow symbolic names for registers\n\ diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 6575f68..88a043f 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2001-10-17 matthew green + + * gas/ppc/altivec.s: New test for AltiVec. + * gas/ppc/altivec.d: New file. + * gas/ppc/ppc.exp: Test altivec.s + 2001-10-16 Hans-Peter Nilsson * gas/sh/err-le.s, gas/sh/err-be.s: New tests. diff --git a/gas/testsuite/gas/ppc/altivec.d b/gas/testsuite/gas/ppc/altivec.d new file mode 100644 index 0000000..6fc1b7e --- /dev/null +++ b/gas/testsuite/gas/ppc/altivec.d @@ -0,0 +1,16 @@ +#as: -m601 -maltivec +#objdump: -Dr +#name: AltiVec tests + +.*: +file format elf32-powerpc + +Disassembly of section \.text: + +00000000 : + 0: 7c 60 06 6c dss 3 + 4: 7e 40 06 6c dssall 2 + 8: 7c 25 22 ac dst r5,r4,1 + c: 7e 08 3a ac dstt r8,r7,0 + 10: 7c 65 32 ec dstst r5,r6,3 + 14: 7e 44 2a ec dststt r4,r5,2 +Disassembly of section \.data: diff --git a/gas/testsuite/gas/ppc/altivec.s b/gas/testsuite/gas/ppc/altivec.s new file mode 100644 index 0000000..40e143d --- /dev/null +++ b/gas/testsuite/gas/ppc/altivec.s @@ -0,0 +1,10 @@ +# PowerPC AltiVec tests +#as: -m601 -maltivec + .section ".text" +start: + dss 3 + dssall 2 + dst 5,4,1 + dstt 8,7,0 + dstst 5,6,3 + dststt 4,5,2 diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 85d5be0..d84ce95 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -27,4 +27,5 @@ if { [istarget powerpc64*-*-*] || [istarget *-*-elf64*]} then { if { [istarget powerpc*-*-*] } then { run_dump_test "simpshft" run_dump_test "booke" + run_dump_test "altivec" } diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 690b19c..ec236b3 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2001-10-17 matthew green + + * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. + 2001-10-12 matthew green * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 26a96ec..c313696 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -98,7 +98,7 @@ extern const int powerpc_num_opcodes; #define PPC_OPCODE_BOOKE (04000) /* Opcode is only supported by 64-bit Motorola BookE processor. */ -#define PPC_OPCODE_BOOKE64 (001000) +#define PPC_OPCODE_BOOKE64 (010000) /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6bb9b7e..09a88f0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2001-10-17 matthew green + + * ppc-opc.c (STRM): New AltiVec operand. + (XDSS): New AltiVec instruction form. + (mtvscr): Correct operand list. + (dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions. + 2001-10-17 Alan Modra * po/POTFILES.in: Regenerate. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 4ff73cd..8aab61b 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -403,8 +403,13 @@ const struct powerpc_operand powerpc_operands[] = #define SR SPRG + 1 { 4, 16, 0, 0, 0 }, + /* The STRM field in an X AltiVec form instruction. */ +#define STRM SR + 1 +#define STRM_MASK (0x3 << 21) + { 2, 21, 0, 0, 0 }, + /* The SV field in a POWER SC form instruction. */ -#define SV SR + 1 +#define SV STRM + 1 { 14, 2, 0, 0, 0 }, /* The TBR field in an XFX form instruction. This is like the SPR @@ -1289,6 +1294,10 @@ extract_tbr (insn, invalid) /* An X form sync instruction with everything filled in except the LS field. */ #define XSYNC_MASK (0xff9fffff) +/* An X form AltiVec dss instruction. */ +#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) +#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) + /* An XFL form instruction. */ #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) @@ -1584,7 +1593,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } }, { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } }, { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, -{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } }, +{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, @@ -2972,10 +2981,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } }, +{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, +{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, + { "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } }, { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, +{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, + { "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } }, { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, @@ -3366,6 +3381,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, +{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, +{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { STRM } }, + { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },