From: Gert Wollny Date: Mon, 18 Jan 2021 17:03:39 +0000 (+0100) Subject: r600: Add flags to INTERP_X and INTERP_Z two-slot ops X-Git-Tag: upstream/21.2.3~9292 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f57ae1e69cfa5328d1520dd8832bf79805932fcb;p=platform%2Fupstream%2Fmesa.git r600: Add flags to INTERP_X and INTERP_Z two-slot ops v2: use the gap in the enum bit field to add the 2-slot bit Signed-off-by: Gert Wollny Part-of: --- diff --git a/src/gallium/drivers/r600/r600_isa.c b/src/gallium/drivers/r600/r600_isa.c index 57b0e04..0a5c4da 100644 --- a/src/gallium/drivers/r600/r600_isa.c +++ b/src/gallium/drivers/r600/r600_isa.c @@ -194,8 +194,8 @@ const struct alu_op_info r600_alu_op_table[] = { {"MULADD_IEEE_PREV", 2, { -1, 0xD5 },{ 0, 0, AF_V, AF_V}, AF_PREV_INTERLEAVE | AF_IEEE }, {"INTERP_XY", 2, { -1, 0xD6 },{ 0, 0, AF_4V, AF_4V}, AF_INTERP }, {"INTERP_ZW", 2, { -1, 0xD7 },{ 0, 0, AF_4V, AF_4V}, AF_INTERP }, - {"INTERP_X", 2, { -1, 0xD8 },{ 0, 0, AF_V, AF_V}, AF_INTERP }, - {"INTERP_Z", 2, { -1, 0xD9 },{ 0, 0, AF_V, AF_V}, AF_INTERP }, + {"INTERP_X", 2, { -1, 0xD8 },{ 0, 0, AF_2V, AF_2V}, AF_INTERP }, + {"INTERP_Z", 2, { -1, 0xD9 },{ 0, 0, AF_2V, AF_2V}, AF_INTERP }, {"STORE_FLAGS", 1, { -1, 0xDA },{ 0, 0, AF_V, AF_V}, 0 }, {"LOAD_STORE_FLAGS", 1, { -1, 0xDB },{ 0, 0, AF_V, AF_V}, 0 }, {"LDS_1A", 2, { -1, 0xDC },{ 0, 0, AF_V, AF_V}, 0 }, diff --git a/src/gallium/drivers/r600/r600_isa.h b/src/gallium/drivers/r600/r600_isa.h index 73694f7..1c098fb 100644 --- a/src/gallium/drivers/r600/r600_isa.h +++ b/src/gallium/drivers/r600/r600_isa.h @@ -47,6 +47,9 @@ enum alu_op_flags AF_4V = (AF_V | AF_4SLOT), AF_VS = (AF_V | AF_S), /* allowed in any slot */ + AF_2SLOT = (1 << 3), + AF_2V = AF_V | AF_2SLOT, /* XY or ZW */ + AF_KILL = (1<<4), AF_PRED = (1<<5), AF_SET = (1<<6), @@ -55,6 +58,7 @@ enum alu_op_flags AF_PREV_INTERLEAVE = (1<<7), AF_MOVA = (1<<8), /* all MOVA instructions */ + AF_IEEE = (1<<10), AF_DST_TYPE_MASK = (3<<11), @@ -107,6 +111,7 @@ enum alu_op_flags /* condition codes - 3 bits */ AF_CC_SHIFT = 29, + AF_CC_MASK = (7U << AF_CC_SHIFT), AF_CC_E = (0U << AF_CC_SHIFT), AF_CC_GT = (1U << AF_CC_SHIFT),