From: Geert Uytterhoeven Date: Wed, 21 Nov 2018 09:43:42 +0000 (+0100) Subject: clk: renesas: r8a7796: Add CPEX clock X-Git-Tag: v5.4-rc1~1882^2~7^2^2~11 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f51389cb6a976e1a6edd0289ea5406c462021bc5;p=platform%2Fkernel%2Flinux-rpi.git clk: renesas: r8a7796: Add CPEX clock Implement support for the CPEX clock on R-Car M3-W. This clock can be selected as a clock source for CMT1 (Compare Match Timer Type 1). Signed-off-by: Geert Uytterhoeven Acked-by: Stephen Boyd --- diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 1056738..12c4558 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -103,6 +103,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1), DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),