From: Sanjay Patel Date: Mon, 13 Dec 2021 15:02:38 +0000 (-0500) Subject: [InstCombine] don't automatically drop poison-generating flags in SimplifyVectorDeman... X-Git-Tag: upstream/15.0.7~23229 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f46a9c8edd4421e875927d6808fea04090e28d37;p=platform%2Fupstream%2Fllvm.git [InstCombine] don't automatically drop poison-generating flags in SimplifyVectorDemandedElts I noticed this while reviewing the test diffs in D115460 (and so the diffs in that patch will be reduced if this one is applied first). This is effectively a revert of 3436dc29239d ( https://reviews.llvm.org/rG3436dc29239d ) - since that commit, we've made several enhancements, so the reasoning there is no longer valid. Specifically, we added a poison value to IR, and we clarified the behavior of undef/poison elements in a shuffle mask: https://llvm.org/docs/LangRef.html#shufflevector-instruction Alive2 seems to agree that the propagation of flags in the test diffs shown here are valid: https://alive2.llvm.org/ce/z/UuY-jr https://alive2.llvm.org/ce/z/GXoMD9 https://alive2.llvm.org/ce/z/nVCyVH Differential Revision: https://reviews.llvm.org/D115526 --- diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index e357a9d..4dc712f 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -1595,12 +1595,6 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V, simplifyAndSetOp(I, 0, DemandedElts, UndefElts); simplifyAndSetOp(I, 1, DemandedElts, UndefElts2); - // Any change to an instruction with potential poison must clear those flags - // because we can not guarantee those constraints now. Other analysis may - // determine that it is safe to re-apply the flags. - if (MadeChange) - BO->dropPoisonGeneratingFlags(); - // Output elements are undefined if both are undefined. Consider things // like undef & 0. The result is known zero, not undef. UndefElts &= UndefElts2; diff --git a/llvm/test/Transforms/InstCombine/X86/x86-muldq-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-muldq-inseltpoison.ll index d7a2c82..68c77ef 100644 --- a/llvm/test/Transforms/InstCombine/X86/x86-muldq-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/X86/x86-muldq-inseltpoison.ll @@ -165,7 +165,7 @@ define <2 x i64> @test_demanded_elts_pmuludq_128(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64> ; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP3]], ; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i64> [[TMP4]], -; CHECK-NEXT: [[TMP7:%.*]] = mul <2 x i64> [[TMP5]], [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <2 x i64> [[TMP5]], [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i64> [[TMP7]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: ret <2 x i64> [[TMP8]] ; diff --git a/llvm/test/Transforms/InstCombine/X86/x86-muldq.ll b/llvm/test/Transforms/InstCombine/X86/x86-muldq.ll index c6e5f47..a26737e7 100644 --- a/llvm/test/Transforms/InstCombine/X86/x86-muldq.ll +++ b/llvm/test/Transforms/InstCombine/X86/x86-muldq.ll @@ -165,7 +165,7 @@ define <2 x i64> @test_demanded_elts_pmuludq_128(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64> ; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP3]], ; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i64> [[TMP4]], -; CHECK-NEXT: [[TMP7:%.*]] = mul <2 x i64> [[TMP5]], [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <2 x i64> [[TMP5]], [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i64> [[TMP7]], <2 x i64> undef, <2 x i32> zeroinitializer ; CHECK-NEXT: ret <2 x i64> [[TMP8]] ; diff --git a/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll b/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll index bca56a8..53f2dd1 100644 --- a/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/shuffle_select-inseltpoison.ll @@ -1413,7 +1413,7 @@ define <4 x i8> @or_add_not_enough_masking(<4 x i8> %v) { ; CHECK-LABEL: @or_add_not_enough_masking( ; CHECK-NEXT: [[V0:%.*]] = lshr <4 x i8> [[V:%.*]], ; CHECK-NEXT: [[T1:%.*]] = or <4 x i8> [[V0]], -; CHECK-NEXT: [[T2:%.*]] = add <4 x i8> [[V0]], +; CHECK-NEXT: [[T2:%.*]] = add nuw nsw <4 x i8> [[V0]], ; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i8> [[T2]], <4 x i8> [[T1]], <4 x i32> ; CHECK-NEXT: ret <4 x i8> [[T3]] ; diff --git a/llvm/test/Transforms/InstCombine/shuffle_select.ll b/llvm/test/Transforms/InstCombine/shuffle_select.ll index 63424a1..219d26d 100644 --- a/llvm/test/Transforms/InstCombine/shuffle_select.ll +++ b/llvm/test/Transforms/InstCombine/shuffle_select.ll @@ -1413,7 +1413,7 @@ define <4 x i8> @or_add_not_enough_masking(<4 x i8> %v) { ; CHECK-LABEL: @or_add_not_enough_masking( ; CHECK-NEXT: [[V0:%.*]] = lshr <4 x i8> [[V:%.*]], ; CHECK-NEXT: [[T1:%.*]] = or <4 x i8> [[V0]], -; CHECK-NEXT: [[T2:%.*]] = add <4 x i8> [[V0]], +; CHECK-NEXT: [[T2:%.*]] = add nuw nsw <4 x i8> [[V0]], ; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x i8> [[T2]], <4 x i8> [[T1]], <4 x i32> ; CHECK-NEXT: ret <4 x i8> [[T3]] ; diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll index 10d6bed..3a6f95a 100644 --- a/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll @@ -204,7 +204,7 @@ define <4 x float> @inselt_shuf_no_demand_bogus_insert_index_in_chain(float %a1, define <3 x i8> @shuf_add(<3 x i8> %x) { ; CHECK-LABEL: @shuf_add( -; CHECK-NEXT: [[BO:%.*]] = add <3 x i8> [[X:%.*]], +; CHECK-NEXT: [[BO:%.*]] = add nsw <3 x i8> [[X:%.*]], ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> ; CHECK-NEXT: ret <3 x i8> [[R]] ; @@ -215,7 +215,7 @@ define <3 x i8> @shuf_add(<3 x i8> %x) { define <3 x i8> @shuf_sub(<3 x i8> %x) { ; CHECK-LABEL: @shuf_sub( -; CHECK-NEXT: [[BO:%.*]] = sub <3 x i8> , [[X:%.*]] +; CHECK-NEXT: [[BO:%.*]] = sub nuw <3 x i8> , [[X:%.*]] ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> ; CHECK-NEXT: ret <3 x i8> [[R]] ; @@ -226,7 +226,7 @@ define <3 x i8> @shuf_sub(<3 x i8> %x) { define <3 x i8> @shuf_mul(<3 x i8> %x) { ; CHECK-LABEL: @shuf_mul( -; CHECK-NEXT: [[BO:%.*]] = mul <3 x i8> [[X:%.*]], +; CHECK-NEXT: [[BO:%.*]] = mul nsw <3 x i8> [[X:%.*]], ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> ; CHECK-NEXT: ret <3 x i8> [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll index 7fba4ff..a513d39 100644 --- a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll +++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll @@ -204,7 +204,7 @@ define <4 x float> @inselt_shuf_no_demand_bogus_insert_index_in_chain(float %a1, define <3 x i8> @shuf_add(<3 x i8> %x) { ; CHECK-LABEL: @shuf_add( -; CHECK-NEXT: [[BO:%.*]] = add <3 x i8> [[X:%.*]], +; CHECK-NEXT: [[BO:%.*]] = add nsw <3 x i8> [[X:%.*]], ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> ; CHECK-NEXT: ret <3 x i8> [[R]] ; @@ -215,7 +215,7 @@ define <3 x i8> @shuf_add(<3 x i8> %x) { define <3 x i8> @shuf_sub(<3 x i8> %x) { ; CHECK-LABEL: @shuf_sub( -; CHECK-NEXT: [[BO:%.*]] = sub <3 x i8> , [[X:%.*]] +; CHECK-NEXT: [[BO:%.*]] = sub nuw <3 x i8> , [[X:%.*]] ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> ; CHECK-NEXT: ret <3 x i8> [[R]] ; @@ -226,7 +226,7 @@ define <3 x i8> @shuf_sub(<3 x i8> %x) { define <3 x i8> @shuf_mul(<3 x i8> %x) { ; CHECK-LABEL: @shuf_mul( -; CHECK-NEXT: [[BO:%.*]] = mul <3 x i8> [[X:%.*]], +; CHECK-NEXT: [[BO:%.*]] = mul nsw <3 x i8> [[X:%.*]], ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> ; CHECK-NEXT: ret <3 x i8> [[R]] ;