From: Richard Osborne <richard@xmos.com>
Date: Sun, 27 Jan 2013 21:26:02 +0000 (+0000)
Subject: [XCore] Add missing l2r instructions.
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f2ecd409297626d672d55c2fdaebbfea8fc2d401;p=platform%2Fupstream%2Fllvm.git

[XCore] Add missing l2r instructions.

These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173629
---

diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td
index 185083a..613f9cb 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.td
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td
@@ -811,7 +811,6 @@ def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
                      [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
 
 // Two operand long
-// getd, testlcl
 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
                        "bitrev $dst, $src",
                        [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
@@ -824,6 +823,12 @@ def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
                     "clz $dst, $src",
                     [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
 
+def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src),
+                     "getd $dst, res[$src]", []>;
+
+def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src),
+                     "getn $dst, res[$src]", []>;
+
 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
                      "setc res[$r], $val",
                      [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
@@ -848,10 +853,16 @@ def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),
                         "setclk res[$src1], $src2",
                         [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
 
+def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
+                      "setn res[$src1], $src2", []>;
+
 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
                         "setrdy res[$src1], $src2",
                         [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
 
+def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src),
+                        "testlcl $dst, res[$src]", []>;
+
 // One operand short
 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
                     "msync res[$a]",
diff --git a/llvm/test/MC/Disassembler/XCore/xcore.txt b/llvm/test/MC/Disassembler/XCore/xcore.txt
index 03b2c9a..21b053b 100644
--- a/llvm/test/MC/Disassembler/XCore/xcore.txt
+++ b/llvm/test/MC/Disassembler/XCore/xcore.txt
@@ -275,6 +275,18 @@
 # CHECK: settw res[r7], r2
 0x9b 0xff 0xec 0x27
 
+# CHECK: getd r8, res[r3]
+0x53 0xff 0xec 0x1f
+
+# CHECK: getn r10, res[r11]
+0xbb 0xff 0xec 0x37
+
+# CHECK: testlcl r2, res[r0]
+0xc8 0xfe 0xec 0x27
+
+# CHECK: setn res[r9], r7
+0x6d 0xff 0xec 0x37
+
 # 3r instructions
 
 # CHECK: add r1, r2, r3