From: Jason Ekstrand <jason@jlekstrand.net>
Date: Mon, 6 May 2019 16:45:46 +0000 (-0500)
Subject: nir: Drop imov/fmov in favor of one mov instruction
X-Git-Tag: upstream/19.3.0~6096
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f2dc0f28728af63e1a79756dab06a7035fecb590;p=platform%2Fupstream%2Fmesa.git

nir: Drop imov/fmov in favor of one mov instruction

The difference between imov and fmov has been a constant source of
confusion in NIR for years.  No one really knows why we have two or when
to use one vs. the other.  The real reason is that they do different
things in the presence of source and destination modifiers.  However,
without modifiers (which many back-ends don't have), they are identical.
Now that we've reworked nir_lower_to_source_mods to leave one abs/neg
instruction in place rather than replacing them with imov or fmov
instructions, we don't need two different instructions at all anymore.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Rob Clark <robdclark@chromium.org>
---

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 53c4ff7..265e3b6 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -572,8 +572,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
 		src[i] = get_alu_src(ctx, instr->src[i], src_components);
 
 	switch (instr->op) {
-	case nir_op_fmov:
-	case nir_op_imov:
+	case nir_op_mov:
 		result = src[0];
 		break;
 	case nir_op_fneg:
diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c
index f392d43..5d7b42d 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -827,8 +827,7 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
         struct qreg result;
 
         switch (instr->op) {
-        case nir_op_fmov:
-        case nir_op_imov:
+        case nir_op_mov:
                 result = vir_MOV(c, src[0]);
                 break;
 
diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp
index 9152b02..59e9764 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -1945,7 +1945,7 @@ nir_visitor::visit(ir_expression *ir)
    case ir_unop_bitcast_d2u64:
    case ir_unop_subroutine_to_int:
       /* no-op */
-      result = nir_imov(&b, srcs[0]);
+      result = nir_mov(&b, srcs[0]);
       break;
    case ir_unop_trunc: result = nir_ftrunc(&b, srcs[0]); break;
    case ir_unop_ceil:  result = nir_fceil(&b, srcs[0]); break;
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 7e51501..15323f9 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -866,7 +866,7 @@ static inline nir_op
 nir_op_vec(unsigned components)
 {
    switch (components) {
-   case  1: return nir_op_imov;
+   case  1: return nir_op_mov;
    case  2: return nir_op_vec2;
    case  3: return nir_op_vec3;
    case  4: return nir_op_vec4;
diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index e14151a..dbbc7e4 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -496,7 +496,7 @@ static inline nir_ssa_def *
 nir_mov_alu(nir_builder *build, nir_alu_src src, unsigned num_components)
 {
    assert(!src.abs && !src.negate);
-   nir_alu_instr *mov = nir_alu_instr_create(build->shader, nir_op_imov);
+   nir_alu_instr *mov = nir_alu_instr_create(build->shader, nir_op_mov);
    nir_ssa_dest_init(&mov->instr, &mov->dest.dest, num_components,
                      nir_src_bit_size(src.src), NULL);
    mov->exact = build->exact;
diff --git a/src/compiler/nir/nir_from_ssa.c b/src/compiler/nir/nir_from_ssa.c
index 92effe5..b406e74 100644
--- a/src/compiler/nir/nir_from_ssa.c
+++ b/src/compiler/nir/nir_from_ssa.c
@@ -551,7 +551,7 @@ emit_copy(nir_builder *b, nir_src src, nir_src dest_src)
    else
       assert(src.reg.reg->num_components >= dest_src.reg.reg->num_components);
 
-   nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_imov);
+   nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
    nir_src_copy(&mov->src[0].src, &src, mov);
    mov->dest.dest = nir_dest_for_reg(dest_src.reg.reg);
    mov->dest.write_mask = (1 << dest_src.reg.reg->num_components) - 1;
@@ -852,7 +852,7 @@ place_phi_read(nir_shader *shader, nir_register *reg,
       }
    }
 
-   nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_imov);
+   nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_mov);
    mov->src[0].src = nir_src_for_ssa(def);
    mov->dest.dest = nir_dest_for_reg(reg);
    mov->dest.write_mask = (1 << reg->num_components) - 1;
@@ -889,7 +889,7 @@ nir_lower_phis_to_regs_block(nir_block *block)
 
       nir_register *reg = create_reg_for_ssa_def(&phi->dest.ssa, impl);
 
-      nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_imov);
+      nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_mov);
       mov->src[0].src = nir_src_for_reg(reg);
       mov->dest.write_mask = (1 << phi->dest.ssa.num_components) - 1;
       nir_ssa_dest_init(&mov->instr, &mov->dest.dest,
@@ -989,7 +989,7 @@ nir_lower_ssa_defs_to_regs_block(nir_block *block)
          nir_register *reg = create_reg_for_ssa_def(&load->def, state.impl);
          nir_ssa_def_rewrite_uses(&load->def, nir_src_for_reg(reg));
 
-         nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_imov);
+         nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_mov);
          mov->src[0].src = nir_src_for_ssa(&load->def);
          mov->dest.dest = nir_dest_for_reg(reg);
          mov->dest.write_mask = (1 << reg->num_components) - 1;
diff --git a/src/compiler/nir/nir_gather_ssa_types.c b/src/compiler/nir/nir_gather_ssa_types.c
index 73bd0f9..fa648fe 100644
--- a/src/compiler/nir/nir_gather_ssa_types.c
+++ b/src/compiler/nir/nir_gather_ssa_types.c
@@ -102,8 +102,7 @@ nir_gather_ssa_types(nir_function_impl *impl,
                assert(alu->dest.dest.is_ssa);
                const nir_op_info *info = &nir_op_infos[alu->op];
                switch (alu->op) {
-               case nir_op_imov:
-               case nir_op_fmov:
+               case nir_op_mov:
                case nir_op_vec2:
                case nir_op_vec3:
                case nir_op_vec4:
diff --git a/src/compiler/nir/nir_lower_bool_to_float.c b/src/compiler/nir/nir_lower_bool_to_float.c
index 68fb650..c48b800 100644
--- a/src/compiler/nir/nir_lower_bool_to_float.c
+++ b/src/compiler/nir/nir_lower_bool_to_float.c
@@ -58,8 +58,8 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
       /* These we expect to have booleans but the opcode doesn't change */
       break;
 
-   case nir_op_b2f32: alu->op = nir_op_fmov; break;
-   case nir_op_b2i32: alu->op = nir_op_fmov; break;
+   case nir_op_b2f32: alu->op = nir_op_mov; break;
+   case nir_op_b2i32: alu->op = nir_op_mov; break;
    case nir_op_f2b1:
    case nir_op_i2b1:
       rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
@@ -92,7 +92,6 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
 
    case nir_op_bcsel: alu->op = nir_op_fcsel; break;
 
-   case nir_op_imov: alu->op = nir_op_fmov; break;
    case nir_op_iand: alu->op = nir_op_fmul; break;
    case nir_op_ixor: alu->op = nir_op_sne; break;
    case nir_op_ior: alu->op = nir_op_fmax; break;
diff --git a/src/compiler/nir/nir_lower_bool_to_int32.c b/src/compiler/nir/nir_lower_bool_to_int32.c
index c8f040c..e331de4 100644
--- a/src/compiler/nir/nir_lower_bool_to_int32.c
+++ b/src/compiler/nir/nir_lower_bool_to_int32.c
@@ -49,7 +49,7 @@ lower_alu_instr(nir_alu_instr *alu)
    assert(alu->dest.dest.is_ssa);
 
    switch (alu->op) {
-   case nir_op_imov:
+   case nir_op_mov:
    case nir_op_vec2:
    case nir_op_vec3:
    case nir_op_vec4:
diff --git a/src/compiler/nir/nir_lower_int_to_float.c b/src/compiler/nir/nir_lower_int_to_float.c
index 439afa0..e31644d 100644
--- a/src/compiler/nir/nir_lower_int_to_float.c
+++ b/src/compiler/nir/nir_lower_int_to_float.c
@@ -60,10 +60,10 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
       /* These we expect to have integers or booleans but the opcode doesn't change */
       break;
 
-   case nir_op_b2f32: alu->op = nir_op_fmov; break;
-   case nir_op_b2i32: alu->op = nir_op_fmov; break;
-   case nir_op_i2f32: alu->op = nir_op_fmov; break;
-   case nir_op_f2i32: alu->op = nir_op_fmov; break;
+   case nir_op_b2f32: alu->op = nir_op_mov; break;
+   case nir_op_b2i32: alu->op = nir_op_mov; break;
+   case nir_op_i2f32: alu->op = nir_op_mov; break;
+   case nir_op_f2i32: alu->op = nir_op_mov; break;
    case nir_op_f2i1:
    case nir_op_f2b1:
    case nir_op_i2b1:
@@ -101,7 +101,6 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
    case nir_op_iadd: alu->op = nir_op_fadd; break;
    case nir_op_isub: alu->op = nir_op_fsub; break;
    case nir_op_imul: alu->op = nir_op_fmul; break;
-   case nir_op_imov: alu->op = nir_op_fmov; break;
    case nir_op_iand: alu->op = nir_op_fmul; break;
    case nir_op_ixor: alu->op = nir_op_sne; break;
    case nir_op_ior: alu->op = nir_op_fmax; break;
diff --git a/src/compiler/nir/nir_lower_locals_to_regs.c b/src/compiler/nir/nir_lower_locals_to_regs.c
index 0316c8a..37e17d5 100644
--- a/src/compiler/nir/nir_lower_locals_to_regs.c
+++ b/src/compiler/nir/nir_lower_locals_to_regs.c
@@ -197,7 +197,7 @@ lower_locals_to_regs_block(nir_block *block,
 
          b->cursor = nir_before_instr(&intrin->instr);
 
-         nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_imov);
+         nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
          mov->src[0].src = get_deref_reg_src(deref, state);
          mov->dest.write_mask = (1 << intrin->num_components) - 1;
          if (intrin->dest.is_ssa) {
@@ -225,7 +225,7 @@ lower_locals_to_regs_block(nir_block *block,
 
          nir_src reg_src = get_deref_reg_src(deref, state);
 
-         nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_imov);
+         nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
          nir_src_copy(&mov->src[0].src, &intrin->src[1], mov);
          mov->dest.write_mask = nir_intrinsic_write_mask(intrin);
          mov->dest.dest.is_ssa = false;
diff --git a/src/compiler/nir/nir_lower_phis_to_scalar.c b/src/compiler/nir/nir_lower_phis_to_scalar.c
index c58a678..bea9dc4 100644
--- a/src/compiler/nir/nir_lower_phis_to_scalar.c
+++ b/src/compiler/nir/nir_lower_phis_to_scalar.c
@@ -235,7 +235,7 @@ lower_phis_to_scalar_block(nir_block *block,
          nir_foreach_phi_src(src, phi) {
             /* We need to insert a mov to grab the i'th component of src */
             nir_alu_instr *mov = nir_alu_instr_create(state->mem_ctx,
-                                                      nir_op_imov);
+                                                      nir_op_mov);
             nir_ssa_dest_init(&mov->instr, &mov->dest.dest, 1, bit_size, NULL);
             mov->dest.write_mask = 1;
             nir_src_copy(&mov->src[0].src, &src->src, state->mem_ctx);
diff --git a/src/compiler/nir/nir_lower_to_source_mods.c b/src/compiler/nir/nir_lower_to_source_mods.c
index 63ef404..c4ba604 100644
--- a/src/compiler/nir/nir_lower_to_source_mods.c
+++ b/src/compiler/nir/nir_lower_to_source_mods.c
@@ -178,7 +178,7 @@ nir_lower_to_source_mods_block(nir_block *block,
          assert(child_src->is_ssa);
          nir_alu_instr *child_alu = nir_instr_as_alu(child_src->parent_instr);
 
-         child_alu->op = nir_op_fmov;
+         child_alu->op = nir_op_mov;
          child_alu->dest.saturate = false;
          /* We could propagate the dest of our instruction to the
           * destinations of the uses here.  However, one quick round of
diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c b/src/compiler/nir/nir_lower_vars_to_ssa.c
index 8239eb0..8771910 100644
--- a/src/compiler/nir/nir_lower_vars_to_ssa.c
+++ b/src/compiler/nir/nir_lower_vars_to_ssa.c
@@ -531,7 +531,7 @@ rename_variables(struct lower_variables_state *state)
                continue;
 
             nir_alu_instr *mov = nir_alu_instr_create(state->shader,
-                                                      nir_op_imov);
+                                                      nir_op_mov);
             mov->src[0].src = nir_src_for_ssa(
                nir_phi_builder_value_get_block_def(node->pb_value, block));
             for (unsigned i = intrin->num_components; i < NIR_MAX_VEC_COMPONENTS; i++)
diff --git a/src/compiler/nir/nir_lower_vec_to_movs.c b/src/compiler/nir/nir_lower_vec_to_movs.c
index 8b24376..8c28611 100644
--- a/src/compiler/nir/nir_lower_vec_to_movs.c
+++ b/src/compiler/nir/nir_lower_vec_to_movs.c
@@ -57,7 +57,7 @@ insert_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader)
 {
    assert(start_idx < nir_op_infos[vec->op].num_inputs);
 
-   nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_imov);
+   nir_alu_instr *mov = nir_alu_instr_create(shader, nir_op_mov);
    nir_alu_src_copy(&mov->src[0], &vec->src[start_idx], mov);
    nir_alu_dest_copy(&mov->dest, &vec->dest, mov);
 
diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py
index 3ea25f3..f6fa462 100644
--- a/src/compiler/nir/nir_opcodes.py
+++ b/src/compiler/nir/nir_opcodes.py
@@ -185,10 +185,7 @@ def unop_reduce(name, output_size, output_type, input_type, prereduce_expr,
 def unop_numeric_convert(name, out_type, in_type, const_expr):
    opcode(name, 0, out_type, [0], [in_type], True, "", const_expr)
 
-# These two move instructions differ in what modifiers they support and what
-# the negate modifier means. Otherwise, they are identical.
-unop("fmov", tfloat, "src0")
-unop("imov", tint, "src0")
+unop("mov", tuint, "src0")
 
 unop("ineg", tint, "-src0")
 unop("fneg", tfloat, "-src0")
diff --git a/src/compiler/nir/nir_opcodes_c.py b/src/compiler/nir/nir_opcodes_c.py
index 96c71a1..c6e5bb3 100644
--- a/src/compiler/nir/nir_opcodes_c.py
+++ b/src/compiler/nir/nir_opcodes_c.py
@@ -40,16 +40,16 @@ nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, nir_rounding_mode rnd
    unsigned dst_bit_size = nir_alu_type_get_type_size(dst);
 
    if (src == dst && src_base == nir_type_float) {
-      return nir_op_fmov;
+      return nir_op_mov;
    } else if (src == dst && src_base == nir_type_bool) {
-      return nir_op_imov;
+      return nir_op_mov;
    } else if ((src_base == nir_type_int || src_base == nir_type_uint) &&
               (dst_base == nir_type_int || dst_base == nir_type_uint) &&
               src_bit_size == dst_bit_size) {
       /* Integer <-> integer conversions with the same bit-size on both
        * ends are just no-op moves.
        */
-      return nir_op_imov;
+      return nir_op_mov;
    }
 
    switch (src_base) {
diff --git a/src/compiler/nir/nir_opt_comparison_pre.c b/src/compiler/nir/nir_opt_comparison_pre.c
index eee4962..221379b 100644
--- a/src/compiler/nir/nir_opt_comparison_pre.c
+++ b/src/compiler/nir/nir_opt_comparison_pre.c
@@ -172,7 +172,7 @@ rewrite_compare_instruction(nir_builder *bld, nir_alu_instr *orig_cmp,
     * will clean these up.  This is similar to nir_replace_instr (in
     * nir_search.c).
     */
-   nir_alu_instr *mov_add = nir_alu_instr_create(mem_ctx, nir_op_imov);
+   nir_alu_instr *mov_add = nir_alu_instr_create(mem_ctx, nir_op_mov);
    mov_add->dest.write_mask = orig_add->dest.write_mask;
    nir_ssa_dest_init(&mov_add->instr, &mov_add->dest.dest,
                      orig_add->dest.dest.ssa.num_components,
@@ -181,7 +181,7 @@ rewrite_compare_instruction(nir_builder *bld, nir_alu_instr *orig_cmp,
 
    nir_builder_instr_insert(bld, &mov_add->instr);
 
-   nir_alu_instr *mov_cmp = nir_alu_instr_create(mem_ctx, nir_op_imov);
+   nir_alu_instr *mov_cmp = nir_alu_instr_create(mem_ctx, nir_op_mov);
    mov_cmp->dest.write_mask = orig_cmp->dest.write_mask;
    nir_ssa_dest_init(&mov_cmp->instr, &mov_cmp->dest.dest,
                      orig_cmp->dest.dest.ssa.num_components,
diff --git a/src/compiler/nir/nir_opt_copy_propagate.c b/src/compiler/nir/nir_opt_copy_propagate.c
index 909839a..0961d6b 100644
--- a/src/compiler/nir/nir_opt_copy_propagate.c
+++ b/src/compiler/nir/nir_opt_copy_propagate.c
@@ -36,8 +36,7 @@ static bool is_move(nir_alu_instr *instr)
 {
    assert(instr->src[0].src.is_ssa);
 
-   if (instr->op != nir_op_fmov &&
-       instr->op != nir_op_imov)
+   if (instr->op != nir_op_mov)
       return false;
 
    if (instr->dest.saturate)
@@ -144,8 +143,7 @@ copy_prop_alu_src(nir_alu_instr *parent_alu_instr, unsigned index)
    nir_ssa_def *def;
    unsigned new_swizzle[NIR_MAX_VEC_COMPONENTS] = {0, 0, 0, 0};
 
-   if (alu_instr->op == nir_op_fmov ||
-       alu_instr->op == nir_op_imov) {
+   if (alu_instr->op == nir_op_mov) {
       for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
          new_swizzle[i] = alu_instr->src[0].swizzle[src->swizzle[i]];
       def = alu_instr->src[0].src.ssa;
diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index f674185..6d488bd 100644
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -400,8 +400,8 @@ opt_split_alu_of_phi(nir_builder *b, nir_loop *loop)
        * should be one of the other two operands, so the result of the bcsel
        * should never be replaced with undef.
        *
-       * nir_op_vec{2,3,4}, nir_op_imov, and nir_op_fmov are excluded because
-       * they can easily lead to infinite optimization loops.
+       * nir_op_vec{2,3,4} and nir_op_mov are excluded because they can easily
+       * lead to infinite optimization loops.
        */
       if (alu->op == nir_op_bcsel ||
           alu->op == nir_op_b32csel ||
@@ -409,8 +409,7 @@ opt_split_alu_of_phi(nir_builder *b, nir_loop *loop)
           alu->op == nir_op_vec2 ||
           alu->op == nir_op_vec3 ||
           alu->op == nir_op_vec4 ||
-          alu->op == nir_op_imov ||
-          alu->op == nir_op_fmov ||
+          alu->op == nir_op_mov ||
           alu_instr_is_comparison(alu) ||
           alu_instr_is_type_conversion(alu))
          continue;
diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c
index a4020c8..09ae3d5 100644
--- a/src/compiler/nir/nir_opt_peephole_select.c
+++ b/src/compiler/nir/nir_opt_peephole_select.c
@@ -108,8 +108,7 @@ block_check_for_allowed_instrs(nir_block *block, unsigned *count,
       case nir_instr_type_alu: {
          nir_alu_instr *mov = nir_instr_as_alu(instr);
          switch (mov->op) {
-         case nir_op_fmov:
-         case nir_op_imov:
+         case nir_op_mov:
          case nir_op_fneg:
          case nir_op_ineg:
          case nir_op_fabs:
diff --git a/src/compiler/nir/nir_opt_remove_phis.c b/src/compiler/nir/nir_opt_remove_phis.c
index 3643112..dd55739 100644
--- a/src/compiler/nir/nir_opt_remove_phis.c
+++ b/src/compiler/nir/nir_opt_remove_phis.c
@@ -35,7 +35,7 @@ get_parent_mov(nir_ssa_def *ssa)
       return NULL;
 
    nir_alu_instr *alu = nir_instr_as_alu(ssa->parent_instr);
-   return (alu->op == nir_op_imov || alu->op == nir_op_fmov) ? alu : NULL;
+   return (alu->op == nir_op_mov) ? alu : NULL;
 }
 
 static bool
diff --git a/src/compiler/nir/nir_opt_undef.c b/src/compiler/nir/nir_opt_undef.c
index bdebf55..1f939e8 100644
--- a/src/compiler/nir/nir_opt_undef.c
+++ b/src/compiler/nir/nir_opt_undef.c
@@ -63,7 +63,7 @@ opt_undef_csel(nir_alu_instr *instr)
       memset(&empty_src, 0, sizeof(empty_src));
       nir_instr_rewrite_src(&instr->instr, &instr->src[1].src, empty_src);
       nir_instr_rewrite_src(&instr->instr, &instr->src[2].src, empty_src);
-      instr->op = nir_op_imov;
+      instr->op = nir_op_mov;
 
       return true;
    }
@@ -80,8 +80,7 @@ opt_undef_vecN(nir_builder *b, nir_alu_instr *alu)
    if (alu->op != nir_op_vec2 &&
        alu->op != nir_op_vec3 &&
        alu->op != nir_op_vec4 &&
-       alu->op != nir_op_fmov &&
-       alu->op != nir_op_imov)
+       alu->op != nir_op_mov)
       return false;
 
    assert(alu->dest.dest.is_ssa);
diff --git a/src/compiler/nir/nir_split_vars.c b/src/compiler/nir/nir_split_vars.c
index 62f3222..2ff8257 100644
--- a/src/compiler/nir/nir_split_vars.c
+++ b/src/compiler/nir/nir_split_vars.c
@@ -1062,8 +1062,7 @@ get_non_self_referential_store_comps(nir_intrinsic_instr *store)
 
    nir_alu_instr *src_alu = nir_instr_as_alu(src_instr);
 
-   if (src_alu->op == nir_op_imov ||
-       src_alu->op == nir_op_fmov) {
+   if (src_alu->op == nir_op_mov) {
       /* If it's just a swizzle of a load from the same deref, discount any
        * channels that don't move in the swizzle.
        */
diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index 30c4a9f..bf3f23f 100644
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -217,7 +217,7 @@ validate_alu_src(nir_alu_instr *instr, unsigned index, validate_state *state)
 {
    nir_alu_src *src = &instr->src[index];
 
-   if (instr->op == nir_op_fmov || instr->op == nir_op_imov)
+   if (instr->op == nir_op_mov)
       assert(!src->abs && !src->negate);
 
    unsigned num_components = nir_src_num_components(src->src);
@@ -322,7 +322,7 @@ validate_alu_dest(nir_alu_instr *instr, validate_state *state)
 {
    nir_alu_dest *dest = &instr->dest;
 
-   if (instr->op == nir_op_fmov || instr->op == nir_op_imov)
+   if (instr->op == nir_op_mov)
       assert(!dest->saturate);
 
    unsigned dest_size = nir_dest_num_components(dest->dest);
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 8f53a7c..f7fb827 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -410,7 +410,7 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
    switch (opcode) {
    case SpvOpAny:
       if (src[0]->num_components == 1) {
-         val->ssa->def = nir_imov(&b->nb, src[0]);
+         val->ssa->def = nir_mov(&b->nb, src[0]);
       } else {
          nir_op op;
          switch (src[0]->num_components) {
@@ -427,7 +427,7 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
 
    case SpvOpAll:
       if (src[0]->num_components == 1) {
-         val->ssa->def = nir_imov(&b->nb, src[0]);
+         val->ssa->def = nir_mov(&b->nb, src[0]);
       } else {
          nir_op op;
          switch (src[0]->num_components) {
diff --git a/src/compiler/spirv/vtn_opencl.c b/src/compiler/spirv/vtn_opencl.c
index f608788..5f0f5ac 100644
--- a/src/compiler/spirv/vtn_opencl.c
+++ b/src/compiler/spirv/vtn_opencl.c
@@ -98,7 +98,7 @@ nir_alu_op_for_opencl_opcode(struct vtn_builder *b, enum OpenCLstd opcode)
    case USub_sat: return nir_op_usub_sat;
    case Trunc: return nir_op_ftrunc;
    /* uhm... */
-   case UAbs: return nir_op_imov;
+   case UAbs: return nir_op_mov;
    default:
       vtn_fail("No NIR equivalent");
    }
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 4cae442..c055f0f 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -332,8 +332,8 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
 	/* We also get mov's with more than one component for mov's so
 	 * handle those specially:
 	 */
-	if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
-		type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
+	if (alu->op == nir_op_mov) {
+		type_t type = TYPE_U32;
 		nir_alu_src *asrc = &alu->src[0];
 		struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
 
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 94d863d..ed5fea7 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -833,7 +833,7 @@ ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
    if (!(dest.write_mask & write_mask))
       return;
 
-   nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_imov);
+   nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
    mov->dest = dest;
    mov->dest.write_mask &= write_mask;
    mov->src[0].src = nir_src_for_ssa(def);
@@ -904,8 +904,8 @@ ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
 {
    ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
    ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
-   ttn_move_dest_masked(b, dest, nir_fmov(b, src[0]), TGSI_WRITEMASK_Z);
-   ttn_move_dest_masked(b, dest, nir_fmov(b, src[1]), TGSI_WRITEMASK_W);
+   ttn_move_dest_masked(b, dest, nir_mov(b, src[0]), TGSI_WRITEMASK_Z);
+   ttn_move_dest_masked(b, dest, nir_mov(b, src[1]), TGSI_WRITEMASK_W);
 }
 
 /* LIT - Light Coefficients
@@ -1520,7 +1520,7 @@ ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
 
 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
    [TGSI_OPCODE_ARL] = 0,
-   [TGSI_OPCODE_MOV] = nir_op_fmov,
+   [TGSI_OPCODE_MOV] = nir_op_mov,
    [TGSI_OPCODE_LIT] = 0,
    [TGSI_OPCODE_RCP] = nir_op_frcp,
    [TGSI_OPCODE_RSQ] = nir_op_frsq,
@@ -1648,7 +1648,7 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
 
    /* XXX: SAMPLE opcodes */
 
-   [TGSI_OPCODE_UARL] = nir_op_imov,
+   [TGSI_OPCODE_UARL] = nir_op_mov,
    [TGSI_OPCODE_UCMP] = 0,
    [TGSI_OPCODE_IABS] = nir_op_iabs,
    [TGSI_OPCODE_ISSG] = nir_op_isign,
diff --git a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
index ddf93a6..219ba75 100644
--- a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
+++ b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
@@ -283,7 +283,7 @@ instr_create_alu(struct ir2_context *ctx, nir_op opcode, unsigned ncomp)
 	} nir_ir2_opc[nir_num_opcodes+1] = {
 		[0 ... nir_num_opcodes - 1] = {-1, -1},
 
-		[nir_op_fmov] = {MAXs, MAXv},
+		[nir_op_mov] = {MAXs, MAXv},
 		[nir_op_fsign] = {-1, CNDGTEv},
 		[nir_op_fnot] = {SETEs, SETEv},
 		[nir_op_for] = {MAXs, MAXv},
@@ -315,9 +315,6 @@ instr_create_alu(struct ir2_context *ctx, nir_op opcode, unsigned ncomp)
 		[nir_op_fsin] = {SIN, -1},
 		/* no fsat, fneg, fabs since source mods deal with those */
 
-		/* some nir passes still generate nir_op_imov */
-		[nir_op_imov] = {MAXs, MAXv},
-
 		/* so we can use this function with non-nir op */
 #define ir2_op_cube nir_num_opcodes
 		[ir2_op_cube] = {-1, CUBEv},
@@ -383,7 +380,7 @@ make_src_noconst(struct ir2_context *ctx, nir_src src)
 
 	if (nir_src_as_const_value(src)) {
 		assert(src.is_ssa);
-		instr = instr_create_alu(ctx, nir_op_fmov, src.ssa->num_components);
+		instr = instr_create_alu(ctx, nir_op_mov, src.ssa->num_components);
 		instr->src[0] = make_src(ctx, src);
 		return ir2_src(instr->idx, 0, IR2_SRC_SSA);
 	}
@@ -509,24 +506,24 @@ load_input(struct ir2_context *ctx, nir_dest *dst, unsigned idx)
 		 * TODO: only components that are required by fragment shader
 		 */
 		instr = instr_create_alu_reg(ctx,
-			ctx->so->is_a20x ? nir_op_fadd : nir_op_fmov, 3, NULL);
+			ctx->so->is_a20x ? nir_op_fadd : nir_op_mov, 3, NULL);
 		instr->src[0] = ir2_src(ctx->f->inputs_count, 0, IR2_SRC_INPUT);
 		instr->src[0].abs = true;
 		/* on a20x, C64 contains the tile offset */
 		instr->src[1] = ir2_src(64, 0, IR2_SRC_CONST);
 
-		instr = instr_create_alu_reg(ctx, nir_op_fmov, 4, instr);
+		instr = instr_create_alu_reg(ctx, nir_op_mov, 4, instr);
 		instr->src[0] = ir2_src(ctx->f->fragcoord, 0, IR2_SRC_INPUT);
 
 		instr = instr_create_alu_reg(ctx, nir_op_frcp, 8, instr);
 		instr->src[0] = ir2_src(ctx->f->fragcoord, IR2_SWIZZLE_Y, IR2_SRC_INPUT);
 
 		unsigned reg_idx = instr->reg - ctx->reg; /* XXX */
-		instr = instr_create_alu_dest(ctx, nir_op_fmov, dst);
+		instr = instr_create_alu_dest(ctx, nir_op_mov, dst);
 		instr->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG);
 		break;
 	default:
-		instr = instr_create_alu_dest(ctx, nir_op_fmov, dst);
+		instr = instr_create_alu_dest(ctx, nir_op_mov, dst);
 		instr->src[0] = ir2_src(idx, 0, IR2_SRC_INPUT);
 		break;
 	}
@@ -576,7 +573,7 @@ store_output(struct ir2_context *ctx, nir_src src, unsigned slot, unsigned ncomp
 		return;
 	}
 
-	instr = instr_create_alu(ctx, nir_op_fmov, ncomp);
+	instr = instr_create_alu(ctx, nir_op_mov, ncomp);
 	instr->src[0] = make_src(ctx, src);
 	instr->alu.export = idx;
 }
@@ -600,7 +597,7 @@ emit_intrinsic(struct ir2_context *ctx, nir_intrinsic_instr *intr)
 		assert(const_offset); /* TODO can be false in ES2? */
 		idx = nir_intrinsic_base(intr);
 		idx += (uint32_t) nir_src_as_const_value(intr->src[0])[0].f32;
-		instr = instr_create_alu_dest(ctx, nir_op_fmov, &intr->dest);
+		instr = instr_create_alu_dest(ctx, nir_op_mov, &intr->dest);
 		instr->src[0] = ir2_src(idx, 0, IR2_SRC_CONST);
 		break;
 	case nir_intrinsic_discard:
@@ -780,7 +777,7 @@ emit_undef(struct ir2_context *ctx, nir_ssa_undef_instr * undef)
 
 	struct ir2_instr *instr;
 
-	instr = instr_create_alu_dest(ctx, nir_op_fmov,
+	instr = instr_create_alu_dest(ctx, nir_op_mov,
 		&(nir_dest) {.ssa = undef->def,.is_ssa = true});
 	instr->src[0] = ir2_src(0, 0, IR2_SRC_CONST);
 }
@@ -843,11 +840,11 @@ extra_position_exports(struct ir2_context *ctx, bool binning)
 
 	/* fragcoord z/w */
 	if (ctx->f->fragcoord >= 0 && !binning) {
-		instr = instr_create_alu(ctx, nir_op_fmov, 1);
+		instr = instr_create_alu(ctx, nir_op_mov, 1);
 		instr->src[0] = ir2_src(wincoord->idx, IR2_SWIZZLE_Z, IR2_SRC_SSA);
 		instr->alu.export = ctx->f->fragcoord;
 
-		instr = instr_create_alu(ctx, nir_op_fmov, 1);
+		instr = instr_create_alu(ctx, nir_op_mov, 1);
 		instr->src[0] = ctx->position;
 		instr->src[0].swizzle = IR2_SWIZZLE_W;
 		instr->alu.export = ctx->f->fragcoord;
diff --git a/src/gallium/drivers/lima/ir/gp/nir.c b/src/gallium/drivers/lima/ir/gp/nir.c
index dcfbc45..49010d3 100644
--- a/src/gallium/drivers/lima/ir/gp/nir.c
+++ b/src/gallium/drivers/lima/ir/gp/nir.c
@@ -129,7 +129,7 @@ static int nir_to_gpir_opcodes[nir_num_opcodes] = {
    [nir_op_fand] = gpir_op_min,
    [nir_op_for] = gpir_op_max,
    [nir_op_fabs] = gpir_op_abs,
-   [nir_op_fmov] = gpir_op_mov,
+   [nir_op_mov] = gpir_op_mov,
 };
 
 static bool gpir_emit_alu(gpir_block *block, nir_instr *ni)
diff --git a/src/gallium/drivers/lima/ir/pp/nir.c b/src/gallium/drivers/lima/ir/pp/nir.c
index bb50385..1d39082 100644
--- a/src/gallium/drivers/lima/ir/pp/nir.c
+++ b/src/gallium/drivers/lima/ir/pp/nir.c
@@ -117,8 +117,7 @@ static int nir_to_ppir_opcodes[nir_num_opcodes] = {
    /* not supported */
    [0 ... nir_last_opcode] = -1,
 
-   [nir_op_fmov] = ppir_op_mov,
-   [nir_op_imov] = ppir_op_mov,
+   [nir_op_mov] = ppir_op_mov,
    [nir_op_fmul] = ppir_op_mul,
    [nir_op_fadd] = ppir_op_add,
    [nir_op_fdot2] = ppir_op_dot2,
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 9054060..a9089ea 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
@@ -2845,8 +2845,7 @@ Converter::visit(nir_alu_instr *insn)
    // those are weird ALU ops and need special handling, because
    //   1. they are always componend based
    //   2. they basically just merge multiple values into one data type
-   case nir_op_imov:
-   case nir_op_fmov:
+   case nir_op_mov:
       if (!insn->dest.dest.is_ssa && insn->dest.dest.reg.reg->num_array_elems) {
          nir_reg_dest& reg = insn->dest.dest.reg;
          uint32_t goffset = regToLmemOffset[reg.reg->index];
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 640e4a5..d8d3751 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -786,7 +786,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
                 ALU_CASE(imax, imax);
                 ALU_CASE(umin, umin);
                 ALU_CASE(umax, umax);
-                ALU_CASE(fmov, fmov);
                 ALU_CASE(ffloor, ffloor);
                 ALU_CASE(fround_even, froundeven);
                 ALU_CASE(ftrunc, ftrunc);
@@ -797,7 +796,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
                 ALU_CASE(isub, isub);
                 ALU_CASE(imul, imul);
                 ALU_CASE(iabs, iabs);
-                ALU_CASE(imov, imov);
+                ALU_CASE(mov, imov);
 
                 ALU_CASE(feq32, feq);
                 ALU_CASE(fne32, fne);
diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index ca94619..ecfdbac 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1128,8 +1128,7 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
         struct qreg result;
 
         switch (instr->op) {
-        case nir_op_fmov:
-        case nir_op_imov:
+        case nir_op_mov:
                 result = qir_MOV(c, src[0]);
                 break;
         case nir_op_fmul:
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 794a38d..87edd9d 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -711,8 +711,7 @@ fs_visitor::prepare_alu_destination_and_sources(const fs_builder &bld,
     * instructions.
     */
    switch (instr->op) {
-   case nir_op_imov:
-   case nir_op_fmov:
+   case nir_op_mov:
    case nir_op_vec2:
    case nir_op_vec3:
    case nir_op_vec4:
@@ -991,8 +990,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
    fs_reg result = prepare_alu_destination_and_sources(bld, instr, op, true);
 
    switch (instr->op) {
-   case nir_op_imov:
-   case nir_op_fmov:
+   case nir_op_mov:
    case nir_op_vec2:
    case nir_op_vec3:
    case nir_op_vec4: {
@@ -1011,7 +1009,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
          if (!(instr->dest.write_mask & (1 << i)))
             continue;
 
-         if (instr->op == nir_op_imov || instr->op == nir_op_fmov) {
+         if (instr->op == nir_op_mov) {
             inst = bld.MOV(offset(temp, bld, i),
                            offset(op[0], bld, instr->src[0].swizzle[i]));
          } else {
diff --git a/src/intel/compiler/brw_nir_analyze_boolean_resolves.c b/src/intel/compiler/brw_nir_analyze_boolean_resolves.c
index fd9e774..f298590 100644
--- a/src/intel/compiler/brw_nir_analyze_boolean_resolves.c
+++ b/src/intel/compiler/brw_nir_analyze_boolean_resolves.c
@@ -129,7 +129,7 @@ analyze_boolean_resolves_block(nir_block *block)
             resolve_status = BRW_NIR_BOOLEAN_NO_RESOLVE;
             break;
 
-         case nir_op_imov:
+         case nir_op_mov:
          case nir_op_inot:
             /* This is a single-source instruction.  Just copy the resolve
              * status from the source.
diff --git a/src/intel/compiler/brw_nir_opt_peephole_ffma.c b/src/intel/compiler/brw_nir_opt_peephole_ffma.c
index 7271bdb..58fabb1 100644
--- a/src/intel/compiler/brw_nir_opt_peephole_ffma.c
+++ b/src/intel/compiler/brw_nir_opt_peephole_ffma.c
@@ -50,8 +50,7 @@ are_all_uses_fadd(nir_ssa_def *def)
       case nir_op_fadd:
          break; /* This one's ok */
 
-      case nir_op_imov:
-      case nir_op_fmov:
+      case nir_op_mov:
       case nir_op_fneg:
       case nir_op_fabs:
          assert(use_alu->dest.dest.is_ssa);
@@ -91,8 +90,7 @@ get_mul_for_src(nir_alu_src *src, unsigned num_components,
       return NULL;
 
    switch (alu->op) {
-   case nir_op_imov:
-   case nir_op_fmov:
+   case nir_op_mov:
       alu = get_mul_for_src(&alu->src[0], alu->dest.dest.ssa.num_components,
                             swizzle, negate, abs);
       break;
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index 027d3d9..39f78fa 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -1091,8 +1091,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
    }
 
    switch (instr->op) {
-   case nir_op_imov:
-   case nir_op_fmov:
+   case nir_op_mov:
       inst = emit(MOV(dst, op[0]));
       inst->saturate = instr->dest.saturate;
       break;
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index 9e45181..269724e 100644
--- a/src/mesa/program/prog_to_nir.c
+++ b/src/mesa/program/prog_to_nir.c
@@ -222,7 +222,7 @@ ptn_get_src(struct ptn_compile *c, const struct prog_src_register *prog_src)
             chans[i] = nir_imm_float(b, 1.0);
          } else {
             assert(swizzle != SWIZZLE_NIL);
-            nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_fmov);
+            nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
             nir_ssa_dest_init(&mov->instr, &mov->dest.dest, 1, 32, NULL);
             mov->dest.write_mask = 0x1;
             mov->src[0] = src;
@@ -262,7 +262,7 @@ ptn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
    if (!(dest.write_mask & write_mask))
       return;
 
-   nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_fmov);
+   nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
    if (!mov)
       return;
 
@@ -336,8 +336,8 @@ ptn_dst(nir_builder *b, nir_alu_dest dest, nir_ssa_def **src)
 {
    ptn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), WRITEMASK_X);
    ptn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), WRITEMASK_Y);
-   ptn_move_dest_masked(b, dest, nir_fmov(b, src[0]), WRITEMASK_Z);
-   ptn_move_dest_masked(b, dest, nir_fmov(b, src[1]), WRITEMASK_W);
+   ptn_move_dest_masked(b, dest, nir_mov(b, src[0]), WRITEMASK_Z);
+   ptn_move_dest_masked(b, dest, nir_mov(b, src[1]), WRITEMASK_W);
 }
 
 /* LIT - Light Coefficients
@@ -647,7 +647,7 @@ static const nir_op op_trans[MAX_OPCODE] = {
    [OPCODE_MAD] = 0,
    [OPCODE_MAX] = nir_op_fmax,
    [OPCODE_MIN] = nir_op_fmin,
-   [OPCODE_MOV] = nir_op_fmov,
+   [OPCODE_MOV] = nir_op_mov,
    [OPCODE_MUL] = nir_op_fmul,
    [OPCODE_POW] = 0,
    [OPCODE_RCP] = 0,
@@ -797,7 +797,7 @@ ptn_emit_instruction(struct ptn_compile *c, struct prog_instruction *prog_inst)
 
    case OPCODE_SWZ:
       /* Extended swizzles were already handled in ptn_get_src(). */
-      ptn_alu(b, nir_op_fmov, dest, src);
+      ptn_alu(b, nir_op_mov, dest, src);
       break;
 
    case OPCODE_NOP: