From: Craig Topper <craig.topper@sifive.com>
Date: Wed, 8 Mar 2023 03:52:57 +0000 (-0800)
Subject: [RISCV] Add test case for Zfa fli.s miscompile. NFC
X-Git-Tag: upstream/17.0.6~15553
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f2c1b1a7f54ee74018d369f449a26e3d0cce5806;p=platform%2Fupstream%2Fllvm.git

[RISCV] Add test case for Zfa fli.s miscompile. NFC

The f32 matching code for fli was hacked to allow the f16 minimum value
to match for the fli.h instruction in the assembler. This was done
because the assembler parses the floating point literal for fli.h,
fli.s, and fli.d as a single precision value.

Unfortunately, this function is also used by CodeGen and causes
this value to be miscompiled for f32.
---

diff --git a/llvm/test/CodeGen/RISCV/float-zfa.ll b/llvm/test/CodeGen/RISCV/float-zfa.ll
index fe8359d..7700f57 100644
--- a/llvm/test/CodeGen/RISCV/float-zfa.ll
+++ b/llvm/test/CodeGen/RISCV/float-zfa.ll
@@ -77,6 +77,15 @@ define float @loadfpimm9() {
   ret float 255.0
 }
 
+; FIXME: This is the f16 minimum value. It should not be supported for f32.
+define float @loadfpimm10() {
+; CHECK-LABEL: loadfpimm10:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fli.s fa0, min
+; CHECK-NEXT:    ret
+  ret float 0.00006103515625
+}
+
 declare float @llvm.minimum.f32(float, float)
 
 define float @fminm_s(float %a, float %b) nounwind {