From: Craig Topper <craig.topper@intel.com>
Date: Tue, 21 Nov 2017 06:28:15 +0000 (+0000)
Subject: [X86] Simplify type constraints for AVX2 masked gather.
X-Git-Tag: llvmorg-6.0.0-rc1~2937
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f26fc823ec081239fa783ea9420fcdbb364f2aea;p=platform%2Fupstream%2Fllvm.git

[X86] Simplify type constraints for AVX2 masked gather.

We don't need separate 32 and 64 node types. We can use SDTCisInt and SDTCisSameSizeAs to ensure the mask size the result type and is integer.

llvm-svn: 318732
---

diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
index 2dc29ca..6f25b30 100644
--- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -1104,72 +1104,67 @@ def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3)
 
 // AVX2 special nodes
 // masked gather of AVX2 where mask elements are i32
-def avx2_x86_masked_gather_32 : SDNode<"X86ISD::MGATHER",
+def avx2_x86_masked_gather : SDNode<"X86ISD::MGATHER",
       SDTypeProfile<2, 3, [
         SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
-        SDTCisPtrTy<4>, SDTCVecEltisVT<1, i32>, SDTCisSameNumEltsAs<0, 1>]>,
+        SDTCisPtrTy<4>, SDTCisInt<1>, SDTCisSameSizeAs<0, 1>,
+        SDTCisSameNumEltsAs<0, 1>]>,
       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 
-def avx2_masked_gather_32 : SDNode<"ISD::MGATHER",
+def avx2_masked_gather : SDNode<"ISD::MGATHER",
       SDTypeProfile<2, 3, [
         SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
-        SDTCisPtrTy<4>, SDTCVecEltisVT<1, i32>, SDTCisSameNumEltsAs<0, 1>]>,
-      [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
-
-// masked gather of AVX2 where mask elements are i64
-def avx2_masked_gather_64 : SDNode<"ISD::MGATHER",
-      SDTypeProfile<2, 3, [
-        SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
-        SDTCisPtrTy<4>, SDTCVecEltisVT<1, i64>, SDTCisSameNumEltsAs<0, 1>]>,
+        SDTCisPtrTy<4>, SDTCisInt<1>, SDTCisSameSizeAs<0, 1>,
+        SDTCisSameNumEltsAs<0, 1>]>,
       [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 
 // dword gathers
 def avx2_mvpgatherdd_ps_xmm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
-  (avx2_masked_gather_32 node:$src1, node:$src2, node:$src3) , [{
+  (avx2_masked_gather node:$src1, node:$src2, node:$src3) , [{
   MaskedGatherSDNode *Mgt = cast<MaskedGatherSDNode>(N);
   return Mgt->getIndex().getValueType() == MVT::v4i32;
 }]>;
 
 def avx2_mvpgatherqd_ps_xmm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
-  (avx2_x86_masked_gather_32 node:$src1, node:$src2, node:$src3) , [{
+  (avx2_x86_masked_gather node:$src1, node:$src2, node:$src3) , [{
   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
   return Mgt->getIndex().getValueType() == MVT::v2i64;
 }]>;
 
 def avx2_mvpgatherdd_ps_ymm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
-  (avx2_masked_gather_32 node:$src1, node:$src2, node:$src3) , [{
+  (avx2_masked_gather node:$src1, node:$src2, node:$src3) , [{
   MaskedGatherSDNode *Mgt = cast<MaskedGatherSDNode>(N);
   return Mgt->getIndex().getValueType() == MVT::v8i32;
 }]>;
 
 def avx2_mvpgatherqd_ps_ymm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
-  (avx2_masked_gather_32 node:$src1, node:$src2, node:$src3) , [{
+  (avx2_masked_gather node:$src1, node:$src2, node:$src3) , [{
   MaskedGatherSDNode *Mgt = cast<MaskedGatherSDNode>(N);
   return Mgt->getIndex().getValueType() == MVT::v4i64;
 }]>;
 
 // qwords
 def avx2_mvpgatherdq_pd_xmm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
-  (avx2_masked_gather_64 node:$src1, node:$src2, node:$src3) , [{
+  (avx2_masked_gather node:$src1, node:$src2, node:$src3) , [{
   MaskedGatherSDNode *Mgt = cast<MaskedGatherSDNode>(N);
   return Mgt->getIndex().getValueType() == MVT::v2i32;
 }]>;
 
 def avx2_mvpgatherqq_pd_xmm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
-  (avx2_masked_gather_64 node:$src1, node:$src2, node:$src3) , [{
+  (avx2_masked_gather node:$src1, node:$src2, node:$src3) , [{
   MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N);
   return Mgt->getIndex().getValueType() == MVT::v2i64 &&
          Mgt->getMemoryVT().is128BitVector();
 }]>;
 
 def avx2_mvpgatherdq_pd_ymm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
-  (avx2_masked_gather_64 node:$src1, node:$src2, node:$src3) , [{
+  (avx2_masked_gather node:$src1, node:$src2, node:$src3) , [{
   MaskedGatherSDNode *Mgt = cast<MaskedGatherSDNode>(N);
   return Mgt->getIndex().getValueType() == MVT::v4i32;
 }]>;
 
 def avx2_mvpgatherqq_pd_ymm : PatFrag<(ops node:$src1, node:$src2, node:$src3),
-  (avx2_masked_gather_64 node:$src1, node:$src2, node:$src3) , [{
+  (avx2_masked_gather node:$src1, node:$src2, node:$src3) , [{
   MaskedGatherSDNode *Mgt = cast<MaskedGatherSDNode>(N);
   return Mgt->getIndex().getValueType() == MVT::v4i64;
 }]>;