From: Sricharan R <r.sricharan@ti.com>
Date: Fri, 8 Nov 2013 10:38:48 +0000 (+0530)
Subject: ARM: dts: doc: Document missing binding for omap5-mpu
X-Git-Tag: v3.13-rc3~5^2~7
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f1e8e3811486b858bcc7190477bc6e4ea8f3488c;p=profile%2Fcommon%2Fkernel-common.git

ARM: dts: doc: Document missing binding for omap5-mpu

The binding and support for omap5-mpu which has a cortex-a15
smp core, gic and integrated L2 cache has been existing for sometime.
So Documenting the missing binding here.

Cc: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
---

diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt
index 1a5a42c..83f405b 100644
--- a/Documentation/devicetree/bindings/arm/omap/mpu.txt
+++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt
@@ -7,10 +7,18 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM.
 Required properties:
 - compatible : Should be "ti,omap3-mpu" for OMAP3
                Should be "ti,omap4-mpu" for OMAP4
+	       Should be "ti,omap5-mpu" for OMAP5
 - ti,hwmods: "mpu"
 
 Examples:
 
+- For an OMAP5 SMP system:
+
+mpu {
+    compatible = "ti,omap5-mpu";
+    ti,hwmods = "mpu"
+};
+
 - For an OMAP4 SMP system:
 
 mpu {