From: Sam Parker Date: Tue, 17 Sep 2019 13:46:26 +0000 (+0000) Subject: [ARM] Fix for buildbots X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f1d069e54df350a807e9b90462485483139327ea;p=platform%2Fupstream%2Fllvm.git [ARM] Fix for buildbots Add --verifymachineinstrs and update the remaining low overhead loop tests. llvm-svn: 372121 --- diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir index bc5f88a..2e3aa0d 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir @@ -1,10 +1,15 @@ -# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s +# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s # CHECK: for.body: # CHECK-NOT: t2DLS # CHECK-NOT: t2LEUpdate --- | - define dso_local arm_aapcscc void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr { + ; ModuleID = 'multiblock-massive.ll' + source_filename = "multiblock-massive.ll" + target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" + target triple = "thumbv8.1m.main" + + define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) { entry: %cmp8 = icmp eq i32 %N, 0 br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader @@ -53,6 +58,9 @@ ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 + ; Function Attrs: nounwind + declare void @llvm.stackprotector(i8*, i8**) #0 + attributes #0 = { nounwind } attributes #1 = { noduplicate nounwind } @@ -65,7 +73,7 @@ legalized: false regBankSelected: false selected: false failedISel: false -tracksRegLiveness: false +tracksRegLiveness: true hasWinCFI: false registers: [] liveins: @@ -106,6 +114,7 @@ machineFunctionInfo: {} body: | bb.0.entry: successors: %bb.2(0x80000000) + liveins: $r0, $r1, $r2, $r3, $r4, $lr frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 @@ -120,6 +129,7 @@ body: | bb.1.for.end: successors: %bb.4(0x04000000), %bb.2(0x7c000000) + liveins: $lr, $r0, $r1, $r2 renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14, $noreg @@ -130,6 +140,7 @@ body: | bb.2.for.body: successors: %bb.3(0x50000000), %bb.1(0x30000000) + liveins: $lr, $r0, $r1, $r2 dead renamable $r3 = SPACE 3072, undef renamable $r0 renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (load 4 from %ir.lsr.iv4) @@ -141,6 +152,7 @@ body: | bb.3.middle.block: successors: %bb.1(0x80000000) + liveins: $lr, $r0, $r1, $r2, $r3, $r12 renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14, $noreg tSTRi killed renamable $r3, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1) diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir index 54973cc..751bcbf 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s +# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s # CHECK-NOT: t2DLS # CHECK: bb.5.for.inc16: # CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 @@ -8,6 +8,11 @@ # CHECK: bb.6.for.cond4.preheader: --- | + ; ModuleID = 'revert-non-header.ll' + source_filename = "revert-non-header.ll" + target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" + target triple = "thumbv8.1m.main" + define void @header_not_target_unrolled_loop(i32* nocapture %v, i32 %n) { entry: %cmp56 = icmp sgt i32 %n, 1 @@ -48,16 +53,16 @@ br label %land.rhs land.rhs: ; preds = %land.rhs.preheader, %for.body8 - %lsr.iv4 = phi i32 [ 0, %land.rhs.preheader ], [ %lsr.iv.next, %for.body8 ] + %lsr.iv4 = phi i32 [ %lsr.iv.next, %for.body8 ], [ 0, %land.rhs.preheader ] %j.051 = phi i32 [ %j.0, %for.body8 ], [ %j.048, %land.rhs.preheader ] %1 = bitcast i32* %lsr.iv2 to i8* %2 = bitcast i32* %lsr.iv to i8* - %uglygep10 = getelementptr i8, i8* %2, i32 %lsr.iv4 - %uglygep1011 = bitcast i8* %uglygep10 to i32* - %tmp9 = load i32, i32* %uglygep1011, align 4 - %uglygep7 = getelementptr i8, i8* %1, i32 %lsr.iv4 - %uglygep78 = bitcast i8* %uglygep7 to i32* - %tmp12 = load i32, i32* %uglygep78, align 4 + %uglygep3 = getelementptr i8, i8* %2, i32 %lsr.iv4 + %uglygep34 = bitcast i8* %uglygep3 to i32* + %tmp9 = load i32, i32* %uglygep34, align 4 + %uglygep1 = getelementptr i8, i8* %1, i32 %lsr.iv4 + %uglygep12 = bitcast i8* %uglygep1 to i32* + %tmp12 = load i32, i32* %uglygep12, align 4 %cmp7 = icmp sgt i32 %tmp9, %tmp12 br i1 %cmp7, label %for.body8, label %for.inc16 @@ -108,7 +113,7 @@ legalized: false regBankSelected: false selected: false failedISel: false -tracksRegLiveness: false +tracksRegLiveness: true hasWinCFI: false registers: [] liveins: @@ -165,6 +170,7 @@ machineFunctionInfo: {} body: | bb.0.entry: successors: %bb.1(0x40000000), %bb.9(0x40000000) + liveins: $r0, $r1, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $lr $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr frame-setup CFI_INSTRUCTION def_cfa_offset 32 @@ -181,18 +187,21 @@ body: | bb.1: successors: %bb.3(0x80000000) + liveins: $r0, $r1 $r9 = tMOVr $r1, 14, $noreg tB %bb.3, 14, $noreg bb.2.for.cond.loopexit: successors: %bb.3(0x7c000000), %bb.9(0x04000000) + liveins: $r0, $r1, $r9, $r12 t2CMPri killed renamable $r12, 4, 14, $noreg, implicit-def $cpsr tBcc %bb.9, 11, killed $cpsr bb.3.for.cond1.preheader: successors: %bb.4(0x40000000), %bb.2(0x40000000) + liveins: $r0, $r1, $r9 renamable $r2 = t2ADDrs $r9, $r9, 251, 14, $noreg, $noreg $r12 = tMOVr killed $r9, 14, $noreg @@ -204,6 +213,7 @@ body: | bb.4.for.cond4.preheader.preheader: successors: %bb.7(0x50000000), %bb.5(0x30000000) + liveins: $lr, $r0, $r1, $r9, $r12 renamable $r3 = t2ADDrs renamable $r0, renamable $r9, 18, 14, $noreg, $noreg renamable $r10 = t2LSLri renamable $r9, 2, 14, $noreg, $noreg @@ -214,6 +224,7 @@ body: | bb.5.for.inc16: successors: %bb.6(0x7c000000), %bb.2(0x04000000) + liveins: $lr, $r0, $r1, $r3, $r5, $r8, $r9, $r10, $r12 renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg renamable $r5, dead $cpsr = tADDi8 killed renamable $r5, 4, 14, $noreg @@ -224,20 +235,23 @@ body: | bb.6.for.cond4.preheader: successors: %bb.7(0x50000000), %bb.5(0x30000000) + liveins: $lr, $r0, $r1, $r3, $r5, $r8, $r9, $r10, $r12 renamable $r7 = nsw t2SUBrr renamable $r8, renamable $r9, 14, $noreg, def $cpsr tBcc %bb.5, 4, killed $cpsr bb.7.land.rhs.preheader: successors: %bb.8(0x80000000) + liveins: $lr, $r0, $r1, $r3, $r5, $r7, $r8, $r9, $r10, $r12 renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg bb.8.land.rhs: successors: %bb.5(0x07e00000), %bb.8(0x78200000) + liveins: $lr, $r0, $r1, $r3, $r5, $r6, $r7, $r8, $r9, $r10, $r12 - renamable $r4 = tLDRr renamable $r3, $r6, 14, $noreg :: (load 4 from %ir.uglygep78) - renamable $r2 = tLDRr renamable $r5, $r6, 14, $noreg :: (load 4 from %ir.uglygep1011) + renamable $r4 = tLDRr renamable $r3, $r6, 14, $noreg :: (load 4 from %ir.uglygep12) + renamable $r2 = tLDRr renamable $r5, $r6, 14, $noreg :: (load 4 from %ir.uglygep34) tCMPr renamable $r2, renamable $r4, 14, $noreg, implicit-def $cpsr t2IT 12, 1, implicit-def $itstate tSTRr killed renamable $r4, renamable $r5, $r6, 12, $cpsr, implicit $itstate :: (store 4 into %ir.5) diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir index 69a5bd3..acb7ebd 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir @@ -1,10 +1,15 @@ -# RUN: llc -mtriple=armv8.1m.main -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s +# RUN: llc -mtriple=armv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s # CHECK: entry: # CHECK: $lr = t2DLS # CHECK: for.body: # CHECK: $lr = t2LEUpdate renamable $lr ---- | +--- | + ; ModuleID = 'size-limit.ll' + source_filename = "size-limit.ll" + target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" + target triple = "thumbv8.1m.main" + define dso_local arm_aapcscc void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) { entry: %cmp8 = icmp eq i32 %N, 0 @@ -26,13 +31,13 @@ %lsr.iv1 = phi i32* [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ] %0 = phi i32 [ %N, %for.body.preheader ], [ %3, %for.body ] %size = call i32 @llvm.arm.space(i32 4070, i32 undef) - %scevgep1 = getelementptr i32, i32* %lsr.iv9, i32 1 - %1 = load i32, i32* %scevgep1, align 4 - %scevgep5 = getelementptr i32, i32* %lsr.iv5, i32 1 - %2 = load i32, i32* %scevgep5, align 4 + %scevgep3 = getelementptr i32, i32* %lsr.iv9, i32 1 + %1 = load i32, i32* %scevgep3, align 4 + %scevgep7 = getelementptr i32, i32* %lsr.iv5, i32 1 + %2 = load i32, i32* %scevgep7, align 4 %mul = mul nsw i32 %2, %1 - %scevgep9 = getelementptr i32, i32* %lsr.iv1, i32 1 - store i32 %mul, i32* %scevgep9, align 4 + %scevgep11 = getelementptr i32, i32* %lsr.iv1, i32 1 + store i32 %mul, i32* %scevgep11, align 4 %scevgep2 = getelementptr i32, i32* %lsr.iv1, i32 1 %scevgep6 = getelementptr i32, i32* %lsr.iv5, i32 1 %scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1 @@ -43,11 +48,16 @@ ; Function Attrs: nounwind declare i32 @llvm.arm.space(i32 immarg, i32) #0 + ; Function Attrs: noduplicate nounwind declare void @llvm.set.loop.iterations.i32(i32) #1 + ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 + ; Function Attrs: nounwind + declare void @llvm.stackprotector(i8*, i8**) #0 + attributes #0 = { nounwind } attributes #1 = { noduplicate nounwind } @@ -60,7 +70,7 @@ legalized: false regBankSelected: false selected: false failedISel: false -tracksRegLiveness: false +tracksRegLiveness: true hasWinCFI: false registers: [] liveins: @@ -101,6 +111,7 @@ machineFunctionInfo: {} body: | bb.0.entry: successors: %bb.1(0x80000000) + liveins: $r0, $r1, $r2, $r3, $r7, $lr frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 @@ -117,12 +128,13 @@ body: | bb.1.for.body: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + liveins: $lr, $r0, $r1, $r2 dead renamable $r3 = SPACE 4070, undef renamable $r0 - renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep1) - renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep5) + renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep3) + renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg - early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep9) + early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep11) renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14, $noreg @@ -131,5 +143,3 @@ body: | tPOP_RET 14, $noreg, def $r7, def $pc ... - - diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir index 9d86f92..a97da0c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/switch.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops -o - +# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-low-overhead-loops --verify-machineinstrs -o - # CHECK: bb.1.for.body.preheader: # CHECK: $lr = t2DLS # CHECK-NOT: t2LoopDec @@ -6,6 +6,11 @@ # CHECK: $lr = t2LEUpdate renamable $lr, %bb.2 --- | + ; ModuleID = 'switch.ll' + source_filename = "switch.ll" + target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" + target triple = "thumbv8.1m.main" + define dso_local arm_aapcscc i32 @search(i8* nocapture readonly %c, i32 %N) { entry: %cmp11 = icmp eq i32 %N, 0 @@ -52,10 +57,17 @@ br i1 %4, label %for.body, label %for.cond.cleanup } - declare void @llvm.set.loop.iterations.i32(i32) #1 - declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 - attributes #1 = { noduplicate nounwind } - attributes #2 = { nounwind } + ; Function Attrs: noduplicate nounwind + declare void @llvm.set.loop.iterations.i32(i32) #0 + + ; Function Attrs: noduplicate nounwind + declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 + + ; Function Attrs: nounwind + declare void @llvm.stackprotector(i8*, i8**) #1 + + attributes #0 = { noduplicate nounwind } + attributes #1 = { nounwind } ... --- @@ -66,7 +78,7 @@ legalized: false regBankSelected: false selected: false failedISel: false -tracksRegLiveness: false +tracksRegLiveness: true hasWinCFI: false registers: [] liveins: @@ -77,8 +89,8 @@ frameInfo: isReturnAddressTaken: false hasStackMap: false hasPatchPoint: false - stackSize: 16 - offsetAdjustment: -8 + stackSize: 8 + offsetAdjustment: 0 maxAlignment: 4 adjustsStack: false hasCalls: false @@ -97,12 +109,6 @@ stack: stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, - stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, - debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: [] @@ -111,19 +117,17 @@ machineFunctionInfo: {} body: | bb.0.entry: successors: %bb.7(0x30000000), %bb.1(0x50000000) + liveins: $r0, $r1, $r4, $lr - frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, $r7, killed $lr, implicit-def $sp, implicit $sp - frame-setup CFI_INSTRUCTION def_cfa_offset 16 + frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 - frame-setup CFI_INSTRUCTION offset $r7, -8 - frame-setup CFI_INSTRUCTION offset $r6, -12 - frame-setup CFI_INSTRUCTION offset $r4, -16 - $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg - frame-setup CFI_INSTRUCTION def_cfa $r7, 8 + frame-setup CFI_INSTRUCTION offset $r4, -8 tCBZ $r1, %bb.7 bb.1.for.body.preheader: successors: %bb.4(0x80000000) + liveins: $r0, $r1 $lr = tMOVr $r1, 14, $noreg t2DoLoopStart killed $r1 @@ -134,6 +138,7 @@ body: | bb.2.for.body: successors: %bb.3(0x80000000) + liveins: $lr, $r0, $r1, $r2, $r3, $r12 tCMPi8 killed renamable $r3, 32, 14, $noreg, implicit-def $cpsr t2IT 0, 8, implicit-def $itstate @@ -141,6 +146,7 @@ body: | bb.3.for.inc: successors: %bb.4(0x7c000000), %bb.8(0x04000000) + liveins: $lr, $r0, $r1, $r2, $r12 renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 1, 14, $noreg renamable $lr = t2LoopDec killed renamable $lr, 1 @@ -149,6 +155,7 @@ body: | bb.4.for.body: successors: %bb.2(0x26666665), %bb.5(0x5999999b) + liveins: $lr, $r0, $r1, $r2, $r12 renamable $r3 = tLDRBi renamable $r0, 0, 14, $noreg :: (load 1 from %ir.lsr.iv1) renamable $r4 = t2SUBri renamable $r3, 108, 14, $noreg, $noreg @@ -157,6 +164,7 @@ body: | bb.5.for.body: successors: %bb.6(0x6db6db6e), %bb.2(0x12492492) + liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r12 renamable $r4 = t2LSLrr renamable $r12, killed renamable $r4, 14, $noreg, $noreg t2TSTri killed renamable $r4, 25, 14, $noreg, implicit-def $cpsr @@ -164,6 +172,7 @@ body: | bb.6.sw.bb: successors: %bb.3(0x80000000) + liveins: $lr, $r0, $r1, $r2, $r12 renamable $r2, dead $cpsr = nsw tADDi8 killed renamable $r2, 1, 14, $noreg tB %bb.3, 14, $noreg @@ -175,8 +184,9 @@ body: | renamable $r1, dead $cpsr = tMOVi8 0, 14, $noreg bb.8.for.cond.cleanup: + liveins: $r1, $r2 + renamable $r0, dead $cpsr = nsw tSUBrr killed renamable $r2, killed renamable $r1, 14, $noreg - tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, implicit killed $r0 + tPOP_RET 14, $noreg, def $r4, def $pc, implicit killed $r0 ... -