From: Paul Burton <paul.burton@imgtec.com>
Date: Thu, 29 Jan 2015 10:04:10 +0000 (+0000)
Subject: MIPS: handle mips64 ST0_KX bit in mips32 start.S
X-Git-Tag: v2015.04-rc1~6^2~2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f1c64a08106db5ce87b6afe76785e2d4fddcff63;p=platform%2Fkernel%2Fu-boot.git

MIPS: handle mips64 ST0_KX bit in mips32 start.S

In preparation for sharing a single copy of start.S between mips32 &
mips64, handle setting the KX bit of the cop0 Status register when the
mips32 start.S is built for mips64.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---

diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 699c59a..3b5b622 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -23,6 +23,7 @@
 
 #ifdef CONFIG_32BIT
 # define MIPS_RELOC	3
+# define STATUS_SET	0
 #endif
 
 #ifdef CONFIG_64BIT
@@ -34,6 +35,7 @@
 	((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
 # endif
 # define MIPS_RELOC	MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
+# define STATUS_SET	ST0_KX
 #endif
 
 	/*
@@ -120,7 +122,7 @@ reset:
 	/* WP(Watch Pending), SW0/1 should be cleared */
 	mtc0	zero, CP0_CAUSE
 
-	setup_c0_status 0 0
+	setup_c0_status STATUS_SET 0
 
 	/* Init Timer */
 	mtc0	zero, CP0_COUNT