From: Pierre-Eric Pelloux-Prayer Date: Tue, 9 Feb 2021 14:10:41 +0000 (+0100) Subject: radeonsi: replace force_cp_dma arg of si_clear_buffer by enum X-Git-Tag: upstream/21.2.3~7739 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f18bceac72b92a066f3f8ebb5ed9f3e86a5f8a7f;p=platform%2Fupstream%2Fmesa.git radeonsi: replace force_cp_dma arg of si_clear_buffer by enum The new enum has 3 values: - SI_CP_DMA_CLEAR_METHOD: equivalent to force_cp_dma = true - SI_COMPUTE_CLEAR_METHOD: to force the clear to use compute - SI_AUTO_SELECT_CLEAR_METHOD: equivalent to force_cp_dma = false No functional change yet, but this will be used later. Reviewed-by: Marek Olšák Part-of: --- diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index 2cb7092eb73..3ad24c1f978 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -1310,7 +1310,7 @@ void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex) uint32_t clear_value = DCC_UNCOMPRESSED; si_clear_buffer(sctx, ptex, tex->surface.dcc_offset, tex->surface.dcc_size, &clear_value, 4, - SI_COHERENCY_CB_META, false); + SI_COHERENCY_CB_META, SI_AUTO_SELECT_CLEAR_METHOD); } } diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index e26797634f9..6394eeb277a 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -259,7 +259,7 @@ bool vi_dcc_clear_level(struct si_context *sctx, struct si_texture *tex, unsigne } si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size, &clear_value, 4, SI_COHERENCY_CB_META, - false); + SI_AUTO_SELECT_CLEAR_METHOD); return true; } @@ -487,7 +487,8 @@ static void si_do_fast_color_clear(struct si_context *sctx, unsigned *buffers, if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) { uint32_t clear_value = 0xCCCCCCCC; si_clear_buffer(sctx, &tex->cmask_buffer->b.b, tex->surface.cmask_offset, - tex->surface.cmask_size, &clear_value, 4, SI_COHERENCY_CB_META, false); + tex->surface.cmask_size, &clear_value, 4, SI_COHERENCY_CB_META, + SI_AUTO_SELECT_CLEAR_METHOD); fmask_decompress_needed = true; } } else { @@ -515,7 +516,8 @@ static void si_do_fast_color_clear(struct si_context *sctx, unsigned *buffers, /* Do the fast clear. */ uint32_t clear_value = 0; si_clear_buffer(sctx, &tex->cmask_buffer->b.b, tex->surface.cmask_offset, - tex->surface.cmask_size, &clear_value, 4, SI_COHERENCY_CB_META, false); + tex->surface.cmask_size, &clear_value, 4, SI_COHERENCY_CB_META, + SI_AUTO_SELECT_CLEAR_METHOD); eliminate_needed = true; } @@ -608,7 +610,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers, sctx->chip_class == GFX8 ? 0xfffff30f : 0xfffc000f; si_clear_buffer(sctx, &zstex->buffer.b.b, zstex->surface.htile_offset, zstex->surface.htile_size, &clear_value, 4, - SI_COHERENCY_DB_META, false); + SI_COHERENCY_DB_META, SI_AUTO_SELECT_CLEAR_METHOD); } /* TC-compatible HTILE only supports depth clears to 0 or 1. */ diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index ca5fd5391c5..f06f1209a80 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -273,7 +273,7 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx, struct pipe_res void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset, uint64_t size, uint32_t *clear_value, uint32_t clear_value_size, - enum si_coherency coher, bool force_cpdma) + enum si_coherency coher, enum si_clear_method method) { if (!size) return; @@ -345,8 +345,12 @@ void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_ compute_min_size = 32 * 1024; } - if (clear_value_size > 4 || (!force_cpdma && clear_value_size == 4 && offset % 4 == 0 && - size > compute_min_size)) { + if (method == SI_AUTO_SELECT_CLEAR_METHOD && ( + clear_value_size > 4 || + (clear_value_size == 4 && offset % 4 == 0 && size > compute_min_size))) { + method = SI_COMPUTE_CLEAR_METHOD; + } + if (method == SI_COMPUTE_CLEAR_METHOD) { si_compute_do_clear_or_copy(sctx, dst, offset, NULL, 0, aligned_size, clear_value, clear_value_size, coher); } else { @@ -385,7 +389,7 @@ static void si_pipe_clear_buffer(struct pipe_context *ctx, struct pipe_resource int clear_value_size) { si_clear_buffer((struct si_context *)ctx, dst, offset, size, (uint32_t *)clear_value, - clear_value_size, SI_COHERENCY_SHADER, false); + clear_value_size, SI_COHERENCY_SHADER, SI_AUTO_SELECT_CLEAR_METHOD); } void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src, @@ -759,7 +763,7 @@ void si_compute_expand_fmask(struct pipe_context *ctx, struct pipe_resource *tex si_clear_buffer(sctx, tex, stex->surface.fmask_offset, stex->surface.fmask_size, (uint32_t *)&fmask_expand_values[log_fragments][log_samples - 1], log_fragments >= 2 && log_samples == 4 ? 8 : 4, - SI_COHERENCY_SHADER, false); + SI_COHERENCY_SHADER, SI_AUTO_SELECT_CLEAR_METHOD); } void si_init_compute_blit_functions(struct si_context *sctx) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index c380dcfe687..6be553a2de0 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -731,7 +731,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign */ uint32_t clear_value = 0; si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, sctx->null_const_buf.buffer->width0, - &clear_value, 4, SI_COHERENCY_SHADER, true); + &clear_value, 4, SI_COHERENCY_SHADER, SI_CP_DMA_CLEAR_METHOD); } sctx->initial_gfx_cs_size = sctx->gfx_cs.current.cdw; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 2aa13948fba..3c1b7885865 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1360,9 +1360,14 @@ unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher, enum si_cache_policy cache_policy); void si_launch_grid_internal(struct si_context *sctx, struct pipe_grid_info *info, void *restore_cs, unsigned flags); +enum si_clear_method { + SI_CP_DMA_CLEAR_METHOD, + SI_COMPUTE_CLEAR_METHOD, + SI_AUTO_SELECT_CLEAR_METHOD +}; void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst, uint64_t offset, uint64_t size, uint32_t *clear_value, uint32_t clear_value_size, - enum si_coherency coher, bool force_cpdma); + enum si_coherency coher, enum si_clear_method method); void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst, uint64_t offset, uint64_t size, unsigned value); void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src, diff --git a/src/gallium/drivers/radeonsi/si_test_blit.c b/src/gallium/drivers/radeonsi/si_test_blit.c index c53dcf9184f..e7222b9127e 100644 --- a/src/gallium/drivers/radeonsi/si_test_blit.c +++ b/src/gallium/drivers/radeonsi/si_test_blit.c @@ -293,7 +293,8 @@ void si_test_blit(struct si_screen *sscreen) /* clear dst pixels */ uint32_t zero = 0; - si_clear_buffer(sctx, dst, 0, sdst->surface.surf_size, &zero, 4, SI_COHERENCY_SHADER, false); + si_clear_buffer(sctx, dst, 0, sdst->surface.surf_size, &zero, 4, + SI_COHERENCY_SHADER, SI_AUTO_SELECT_CLEAR_METHOD); memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size); /* preparation */