From: Dave Airlie Date: Mon, 25 Mar 2019 20:15:27 +0000 (+1000) Subject: Merge tag 'drm-intel-next-2019-03-20' of git://anongit.freedesktop.org/drm/drm-intel... X-Git-Tag: v5.4-rc1~971^2~40 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f144e67b0e683cbb2c476b20a93e27aa1cd9d458;p=platform%2Fkernel%2Flinux-rpi.git Merge tag 'drm-intel-next-2019-03-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next UAPI Changes: - Report an error early instead of SIGBUS later when mmap beyond BO size Core Changes: - This includes backmerge of drm-next and two merges of Maarten's topic/hdr-formats Driver Changes: - Add Comet Lake (Gen9) PCI IDs to Coffee Lake ID list (Anusha) - Add missing ICL PCI ID (Jose) - Fix legacy gamma mode for ICL (Ville) - Assume eDP is present on port A when there is no VBT (Thomas) - Corrections to eDP training patterns (Jose) - Fix PSR2 selective update corruption after PSR1 setup (Jose) - Fix CRC mismatch error for DP link layer compliance (Aditya) - Fix CNL DPLL readout and clean up code (Ville) - Turn off the CUS when turning off a HDR plane (Ville) - Avoid a race with execlist tasklet during race (Chris) - Add missing CSC readout and clean up code (Ville) - Avoid unnecessary wakeref during debugfs/drop_caches/set (Chris, Caz) - Hold references to ring/HW context/context explicitly when used (Chris) - Assume next platforms inherit old platform (Rodrigo) - Use HWS indices rather than addresses for breadcrumbs (Chris) - Add REG_BIT/REG_GENMASK and REG_FIELD_PREP macros (Jani) - Convert crept in C99 types to kernel fixed size types (Jani) - Avoid passing full dev_priv in forcewake functions (Daniele) - Reset GuC on GPU reset (Sujaritha) - Rework MG and Combo PLLs to vfuncs (Lucas) - Explicitly track ppGTT size (Chris, Bob) - Coding style improvements and code modularization (Ville) - Selftest and debugging improvements (Chris) Signed-off-by: Dave Airlie # Conflicts: # drivers/gpu/drm/i915/intel_hdmi.c From: Joonas Lahtinen Link: https://patchwork.freedesktop.org/patch/msgid/20190325124925.GA12726@jlahtine-desk.ger.corp.intel.com --- f144e67b0e683cbb2c476b20a93e27aa1cd9d458 diff --cc drivers/gpu/drm/i915/intel_hdmi.c index 765718b,07893ad..2676778 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@@ -469,39 -638,70 +638,72 @@@ static void intel_write_infoframe(struc buffer[3] = 0; len++; - intel_dig_port->write_infoframe(encoder, - crtc_state, - frame->any.type, buffer, len); + intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); } - static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state) + void intel_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + enum hdmi_infoframe_type type, + union hdmi_infoframe *frame) { + struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); + u8 buffer[VIDEO_DIP_DATA_SIZE]; + int ret; + + if ((crtc_state->infoframes.enable & + intel_hdmi_infoframe_enable(type)) == 0) + return; + + intel_dig_port->read_infoframe(encoder, crtc_state, + type, buffer, sizeof(buffer)); + + /* Fill the 'hole' (see big comment above) at position 3 */ + memmove(&buffer[1], &buffer[0], 3); + + /* see comment above for the reason for this offset */ + ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); + if (ret) { + DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type); + return; + } + + if (frame->any.type != type) + DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", + frame->any.type, type); + } + + static bool + intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state) + { + struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; - union hdmi_infoframe frame; + struct drm_connector *connector = conn_state->connector; int ret; - ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, - conn_state->connector, + if (!crtc_state->has_infoframe) + return true; + + crtc_state->infoframes.enable |= + intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); + + ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, adjusted_mode); - if (ret < 0) { - DRM_ERROR("couldn't fill AVI infoframe\n"); - return; - } + if (ret) + return false; if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) - frame.avi.colorspace = HDMI_COLORSPACE_YUV420; + frame->colorspace = HDMI_COLORSPACE_YUV420; else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) - frame.avi.colorspace = HDMI_COLORSPACE_YUV444; + frame->colorspace = HDMI_COLORSPACE_YUV444; else - frame.avi.colorspace = HDMI_COLORSPACE_RGB; + frame->colorspace = HDMI_COLORSPACE_RGB; - drm_hdmi_avi_infoframe_colorspace(&frame.avi, conn_state); ++ drm_hdmi_avi_infoframe_colorspace(frame, conn_state); + - drm_hdmi_avi_infoframe_quant_range(&frame.avi, - conn_state->connector, + drm_hdmi_avi_infoframe_quant_range(frame, connector, adjusted_mode, crtc_state->limited_color_range ? HDMI_QUANTIZATION_RANGE_LIMITED : diff --cc drivers/gpu/drm/i915/intel_sprite.c index 53174d5,aee4def..3f2055f --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@@ -1821,12 -1837,12 +1837,12 @@@ static const u32 icl_plane_formats[] = DRM_FORMAT_Y210, DRM_FORMAT_Y212, DRM_FORMAT_Y216, - DRM_FORMAT_Y410, - DRM_FORMAT_Y412, - DRM_FORMAT_Y416, + DRM_FORMAT_XVYU2101010, + DRM_FORMAT_XVYU12_16161616, + DRM_FORMAT_XVYU16161616, }; - static const uint32_t icl_hdr_plane_formats[] = { + static const u32 icl_hdr_plane_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, @@@ -1906,12 -1922,12 +1922,12 @@@ static const u32 icl_planar_formats[] DRM_FORMAT_Y210, DRM_FORMAT_Y212, DRM_FORMAT_Y216, - DRM_FORMAT_Y410, - DRM_FORMAT_Y412, - DRM_FORMAT_Y416, + DRM_FORMAT_XVYU2101010, + DRM_FORMAT_XVYU12_16161616, + DRM_FORMAT_XVYU16161616, }; - static const uint32_t icl_hdr_planar_formats[] = { + static const u32 icl_hdr_planar_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888,