From: Danylo Piliaiev <dpiliaiev@igalia.com>
Date: Fri, 11 Nov 2022 15:40:53 +0000 (+0100)
Subject: tu: Implement VK_EXT_post_depth_coverage
X-Git-Tag: upstream/23.3.3~16594
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=f1305d49d913ee9d3b297a6ce76ef7156483cf96;p=platform%2Fupstream%2Fmesa.git

tu: Implement VK_EXT_post_depth_coverage

Passes:
 dEQP-VK.pipeline.monolithic.multisample.sample_mask_with_depth_test.*
 KHR-GL45.post_depth_coverage_tests.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19682>
---

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 28eada2..3db225e 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -5004,6 +5004,10 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
        !ctx->s->info.fs.early_fragment_tests)
       ctx->so->no_earlyz |= ctx->s->info.writes_memory;
 
+   if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
+       ctx->s->info.fs.post_depth_coverage)
+      so->post_depth_coverage = true;
+
 out:
    if (ret) {
       if (so->ir)
diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index 726a3ca..a644850 100644
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -694,6 +694,8 @@ struct ir3_shader_variant {
 
    bool per_samp;
 
+   bool post_depth_coverage;
+
    /* Are we using split or merged register file? */
    bool mergedregs;
 
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 9d09406..7c6930d 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1976,7 +1976,7 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
 		<!-- enable bits for various FS sysvalue regs: -->
 		<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
-		<bitfield name="UNK1" pos="1" type="boolean"/>
+		<bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/>
 		<bitfield name="FACENESS" pos="2" type="boolean"/>
 		<bitfield name="SAMPLEID" pos="3" type="boolean"/>
 		<bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>
diff --git a/src/freedreno/vulkan/tu_device.c b/src/freedreno/vulkan/tu_device.c
index fd66bd7..295b796 100644
--- a/src/freedreno/vulkan/tu_device.c
+++ b/src/freedreno/vulkan/tu_device.c
@@ -242,6 +242,7 @@ get_device_extensions(const struct tu_physical_device *device,
       .EXT_mutable_descriptor_type = true,
       .KHR_pipeline_library = true,
       .EXT_graphics_pipeline_library = true,
+      .EXT_post_depth_coverage = true,
    };
 }
 
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 075988c..0993c96 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -1578,6 +1578,7 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
          CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
          CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
          CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_RENDER_CONTROL1_CENTERRHW) |
+         COND(fs->post_depth_coverage, A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE)  |
          COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
 
    tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
diff --git a/src/freedreno/vulkan/tu_shader.c b/src/freedreno/vulkan/tu_shader.c
index 0dc9219..5fd5f31 100644
--- a/src/freedreno/vulkan/tu_shader.c
+++ b/src/freedreno/vulkan/tu_shader.c
@@ -76,6 +76,7 @@ tu_spirv_to_nir(struct tu_device *dev,
          .subgroup_shuffle = true,
          .subgroup_arithmetic = true,
          .physical_storage_buffer_address = true,
+         .post_depth_coverage = true,
       },
    };